Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
670 of 792
NXP Semiconductors
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
5.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
19:17 CLKS
000
This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
11 clocks / 10 bits
000
001
10 clocks / 9 bits
010
9 clocks / 8 bits
011
8 clocks / 7 bits
100
7 clocks / 6 bits
101
6 clocks / 5 bits
110
5 clocks / 4 bits
111
4 clocks / 3 bits
20
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
reserved bit is not defined.
NA
21
PDN
1
The A/D converter is operational.
0
0
The A/D converter is in power-down mode.
23:22 -
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
reserved bit is not defined.
NA
26:24 START
000
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
started:
No start (this value should be used when clearing PDN to 0).
0
001
Start conversion now.
010
Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0.
011
Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1.
100
Start conversion when the edge selected by bit 27 occurs on MAT0.1.
101
Start conversion when the edge selected by bit 27 occurs on MAT0.3.
110
Start conversion when the edge selected by bit 27 occurs on MAT1.0.
111
Start conversion when the edge selected by bit 27 occurs on MAT1.1.
27
EDGE
1
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
0
0
Start conversion on a rising edge on the selected CAP/MAT signal.
31:28 -
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
reserved bit is not defined.
NA
Table 594: A/D Control Register (AD0CR - address 0xE003 4000) bit description
Bit
Symbol
Value Description
Reset
Value
Value