Nxp Semiconductors UM10237 用户手册
UM10237_2
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User manual
Rev. 02 — 19 December 2008
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NXP Semiconductors
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
5.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to
0xE003 402C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 597: A/D Interrupt Enable Register (AD0INTEN - address 0xE003 400C) bit description
Bit
Symbol
Description
Reset
Value
Value
7:0
ADINTEN 7:0
These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
0x00
8
ADGINTEN
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
1
31:9 Unused
Unused, always 0.
0
Table 598: A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0xE003 4010 to
0xE003 402C) bit description
Bit
Symbol
Description
Reset
Value
Value
5:0
Unused
Unused, always 0.
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
room for future, higher-resolution ADCs.
0
15:6
V/V
REF
When DONE is 1, this field contains a binary fraction representing the
voltage on the Ain pin, divided by the voltage on the Vref pin. Zero in
the field indicates that the voltage on the Ain pin was less than, equal
to, or close to that on V
voltage on the Ain pin, divided by the voltage on the Vref pin. Zero in
the field indicates that the voltage on the Ain pin was less than, equal
to, or close to that on V
REF
, while 0x3FF indicates that the voltage on
Ain was close to, equal to, or greater than that on Vref.
NA
29:16 Unused
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
0
30
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the LS bits.This bit is cleared by reading this register.
the result in the LS bits.This bit is cleared by reading this register.
0
31
DONE
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
when this register is read.
0