Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
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NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.1.2 Interrupt Terminal Count Status Register (DMACIntTCStatus - 0xFFE0 4004)
The DMACIntTCStatus Register is read-only and indicates the status of the terminal count
after masking.
after masking.
shows the bit assignments of the DMACIntTCStatus
Register.
6.1.3 Interrupt Terminal Count Clear Register (DMACIntClear - 0xFFE0 4008)
The DMACIntTCClear Register is write-only and clears a terminal count interrupt request.
When writing to this register, each data bit that is set HIGH causes the corresponding bit
in the status register to be cleared. Data bits that are LOW have no effect on the
corresponding bit in the register.
When writing to this register, each data bit that is set HIGH causes the corresponding bit
in the status register to be cleared. Data bits that are LOW have no effect on the
corresponding bit in the register.
shows the bit assignments of the
DMACIntTCClear Register.
6.1.4 Interrupt Error Status Register (DMACIntErrorStatus - 0xFFE0 400C)
The DMACIntErrorStatus Register is read-only and indicates the status of the error
request after masking.
request after masking.
shows the bit assignments of the
DMACIntErrorStatus Register.
Table 654. Interrupt Status register (DMACIntStatus - address 0xFFE0 4000) bit description
Bit
Symbol
Description
Reset
Value
Value
0
IntStatus0
Status of channel 0 interrupts after masking.
0
1
IntStatus1
Status of channel 1 interrupts after masking.
0
31:2
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
Table 655. Interrupt Terminal Count Status register (DMACIntTCStatus - address
0xFFE0 4004) bit description
Bit
Symbol
Description
Reset
Value
Value
0
IntTCStatus0
Terminal count interrupt request status for channel 0.
0
1
IntTCStatus1
Terminal count interrupt request status for channel 1.
0
31:2
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
Table 656. Interrupt Terminal Count Clear register (DMACIntClear - address 0xFFE0 4008) bit
description
Bit
Symbol
Description
Reset
Value
Value
0
IntTCClear0
Writing a 1 clears the terminal count interrupt request for
channel 0 (IntTCStatus0).
channel 0 (IntTCStatus0).
-
1
IntTCClear1
Writing a 1 clears the terminal count interrupt request for
channel 1 (IntTCStatus1).
channel 1 (IntTCStatus1).
-
31:2
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA