Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

For a peripheral-to-memory or memory-to-peripheral DMA flow the following sequence 
occurs:

1. Program and enable the DMA channel.

2. Wait for a DMA request.

3. The GPDMA starts transferring data when:

– The DMA request goes active.

– The DMA stream has the highest pending priority.

– The GPDMA is the bus master of the AHB bus.

4. If an error occurs while transferring the data, an error interrupt is generated and 

disables the DMA stream, and the flow sequence ends.

5. Decrement the transfer count if the GPDMA is performing the flow control.

6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA 

is performing flow control, or by the peripheral sending a DMA request if the 
peripheral is performing flow control):

– The GPDMA responds with a DMA acknowledge.

– The terminal count interrupt is generated (this interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, 

DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go back to 
step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow 
sequence ends.

For a peripheral-to-peripheral DMA flow the following sequence occurs:

1. Program and enable the DMA channel.

2. Wait for a source DMA request.

3. The GPDMA starts transferring data when:

– The DMA request goes active.

Memory-to-peripheral

Peripheral

GPDMA

Memory-to-peripheral

Peripheral

Peripheral

Peripheral-to-memory

Peripheral

GPDMA

Peripheral-to-memory

Peripheral

Peripheral

Memory-to-memory

GPDMA

GPDMA

Source peripheral to destination 
peripheral

Source peripheral and 
destination peripheral

Source peripheral

Source peripheral to destination 
peripheral

Source peripheral and 
destination peripheral

Destination peripheral

Source peripheral to destination 
peripheral

Source peripheral and 
destination peripheral

GPDMA