Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
774 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
Fig 89. Message overwritten indicated by message lost517
Fig 90. Clearing message lost . . . . . . . . . . . . . . . . . . . .518
Fig 91. Detailed example of acceptance filter tables and ID
Fig 90. Clearing message lost . . . . . . . . . . . . . . . . . . . .518
Fig 91. Detailed example of acceptance filter tables and ID
Fig 95. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .535
Fig 96. Texas Instruments Synchronous Serial Frame
Fig 96. Texas Instruments Synchronous Serial Frame
Fig 98. SPI frame format with CPOL=0 and CPHA=1 . .540
Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 101. Microwire frame format (single transfer) . . . . . .543
Fig 102. Microwire frame format (continuos transfers) . .544
Fig 103. Microwire frame format setup and hold details .544
Fig 104. Multimedia card system . . . . . . . . . . . . . . . . . . .552
Fig 105. Secure digital memory card connection. . . . . . .553
Fig 106. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
Fig 107. Command path state machine . . . . . . . . . . . . . .555
Fig 108. MCI command transfer . . . . . . . . . . . . . . . . . . .555
Fig 109. Data path state machine . . . . . . . . . . . . . . . . . .558
Fig 110. Pending command start . . . . . . . . . . . . . . . . . . .560
Fig 111. I
Fig 102. Microwire frame format (continuos transfers) . .544
Fig 103. Microwire frame format setup and hold details .544
Fig 104. Multimedia card system . . . . . . . . . . . . . . . . . . .552
Fig 105. Secure digital memory card connection. . . . . . .553
Fig 106. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
Fig 107. Command path state machine . . . . . . . . . . . . . .555
Fig 108. MCI command transfer . . . . . . . . . . . . . . . . . . .555
Fig 109. Data path state machine . . . . . . . . . . . . . . . . . .558
Fig 110. Pending command start . . . . . . . . . . . . . . . . . . .560
Fig 111. I
C bus configuration . . . . . . . . . . . . . . . . . . . . .573
Fig 112. Format in the Master Transmitter mode. . . . . . .575
Fig 113. Format of Master Receive mode . . . . . . . . . . . .575
Fig 114. A master receiver switch to master Transmitter after
Fig 113. Format of Master Receive mode . . . . . . . . . . . .575
Fig 114. A master receiver switch to master Transmitter after
Fig 115. Format of Slave Receiver mode . . . . . . . . . . . .576
Fig 116. Format of Slave Transmitter mode . . . . . . . . . .577
Fig 117. I
Fig 116. Format of Slave Transmitter mode . . . . . . . . . .577
Fig 117. I
C Bus serial interface block diagram. . . . . . . .578
Fig 118. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .579
Fig 119. Serial clock synchronization. . . . . . . . . . . . . . . .580
Fig 120. Format and States in the Master Transmitter
Fig 119. Serial clock synchronization. . . . . . . . . . . . . . . .580
Fig 120. Format and States in the Master Transmitter
Fig 122. Format and States in the Slave Receiver mode.592
Fig 123. Format and States in the Slave Transmitter
Fig 123. Format and States in the Slave Transmitter
C bus . . . . . . . . . . . .602
S modes. . . . . . . . .620
Fig 131. Timer block diagram . . . . . . . . . . . . . . . . . . . . . 631
Fig 132. PWM block diagram . . . . . . . . . . . . . . . . . . . . . 634
Fig 133. Sample PWM waveforms . . . . . . . . . . . . . . . . . 636
Fig 134. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . 648
Fig 135. RTC prescaler block diagram . . . . . . . . . . . . . . 659
Fig 136. RTC 32 kHz crystal oscillator circuit . . . . . . . . . 661
Fig 137. Watchdog block diagram. . . . . . . . . . . . . . . . . . 666
Fig 138. Map of lower memory after reset . . . . . . . . . . . 677
Fig 139. Boot process flowchart . . . . . . . . . . . . . . . . . . . 680
Fig 140. IAP parameter passing . . . . . . . . . . . . . . . . . . . 692
Fig 141. Map of lower memory after reset for flashless
Fig 132. PWM block diagram . . . . . . . . . . . . . . . . . . . . . 634
Fig 133. Sample PWM waveforms . . . . . . . . . . . . . . . . . 636
Fig 134. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . 648
Fig 135. RTC prescaler block diagram . . . . . . . . . . . . . . 659
Fig 136. RTC 32 kHz crystal oscillator circuit . . . . . . . . . 661
Fig 137. Watchdog block diagram. . . . . . . . . . . . . . . . . . 666
Fig 138. Map of lower memory after reset . . . . . . . . . . . 677
Fig 139. Boot process flowchart . . . . . . . . . . . . . . . . . . . 680
Fig 140. IAP parameter passing . . . . . . . . . . . . . . . . . . . 692
Fig 141. Map of lower memory after reset for flashless
Fig 142. Boot process flowchart . . . . . . . . . . . . . . . . . . . 700
Fig 143. IAP parameter passing . . . . . . . . . . . . . . . . . . . 708
Fig 144. GPDMA block diagram . . . . . . . . . . . . . . . . . . . 713
Fig 145. Example of GPDMA in a system. . . . . . . . . . . . 714
Fig 146. LLI example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Fig 147. EmbeddedICE debug environment block
Fig 143. IAP parameter passing . . . . . . . . . . . . . . . . . . . 708
Fig 144. GPDMA block diagram . . . . . . . . . . . . . . . . . . . 713
Fig 145. Example of GPDMA in a system. . . . . . . . . . . . 714
Fig 146. LLI example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Fig 147. EmbeddedICE debug environment block