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UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
775 of
792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
5.
Contents
Chapter 1: LPC24XX Introductory information
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
How to read this manual . . . . . . . . . . . . . . . . . . 3
3
LPC2400 features. . . . . . . . . . . . . . . . . . . . . . . . 4
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1
LPC2458 ordering options . . . . . . . . . . . . . . . . 6
5.2
LPC2460 ordering options . . . . . . . . . . . . . . . . 6
5.3
LPC2468 ordering options . . . . . . . . . . . . . . . . 7
5.4
LPC2470 ordering options . . . . . . . . . . . . . . . . 7
5.5
LPC2478 ordering options . . . . . . . . . . . . . . . . 8
6
Architectural overview . . . . . . . . . . . . . . . . . . . 8
7
On-chip flash programming memory
(LPC2458/68/78). . . . . . . . . . . . . . . . . . . . . . . . . 9
8
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 10
9
LPC2458 block diagram . . . . . . . . . . . . . . . . . . 11
10
LPC2420/60 block diagram. . . . . . . . . . . . . . . 12
11
LPC2468 block diagram . . . . . . . . . . . . . . . . . 13
12
LPC2470 block diagram . . . . . . . . . . . . . . . . . 14
13
LPC2478 block diagram . . . . . . . . . . . . . . . . . 15
Chapter 2: LPC24XX Memory mapping
1
How to read this chapter . . . . . . . . . . . . . . . . . 16
2
Memory map and peripheral addressing. . . . 16
3
Memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
APB peripheral addresses . . . . . . . . . . . . . . . 22
5
LPC2400 memory re-mapping and boot ROM 23
5.1
Memory map concepts and operating modes. 23
5.2
Memory re-mapping. . . . . . . . . . . . . . . . . . . . 24
6
Memory mapping control . . . . . . . . . . . . . . . . 25
6.1
Memory Mapping Control Register (MEMMAP -
0xE01F C040) . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2
Memory mapping control usage notes. . . . . . 25
7
Prefetch abort and data abort exceptions . . 27
Chapter 3: LPC24XX System control
1
Summary of system control block functions 28
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 28
3
Register description . . . . . . . . . . . . . . . . . . . . 28
3.1
External interrupt inputs . . . . . . . . . . . . . . . . . 29
3.1.1
Register description . . . . . . . . . . . . . . . . . . . . 29
3.1.2
External Interrupt flag register (EXTINT -
0xE01F C140) . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.3
External Interrupt Mode register (EXTMODE -
0xE01F C148) . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.4
External Interrupt Polarity register (EXTPOLAR -
0xE01F C14C) . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1
Reset Source Identification Register (RSIR -
0xE01F C180) . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3
Other system controls and status flags . . . . . 35
3.3.1
System Controls and Status register (SCS -
0xE01F C1A0) . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4
AHB Configuration . . . . . . . . . . . . . . . . . . . . . 36
3.4.1
AHB Arbiter Configuration register 1 (AHBCFG1
- 0xE01F C188) . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.1.1
Examples of AHB1 settings . . . . . . . . . . . . . . 37
3.4.2
AHB Arbiter Configuration register 2 (AHBCFG2 -
0xE01F C18C) . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.2.1
Examples of AHB2 settings . . . . . . . . . . . . . . 39
4
Brown-out detection . . . . . . . . . . . . . . . . . . . . 40
5
Code security vs. debugging . . . . . . . . . . . . . 40
Chapter 4: LPC24XX Clocking and power control
1
Summary of clocking and power control
functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1
Internal RC oscillator . . . . . . . . . . . . . . . . . . . 43
2.2
Main oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 43
2.3
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 45
3
Register description . . . . . . . . . . . . . . . . . . . . 45
3.1
Clock source selection multiplexer . . . . . . . . . 45
3.1.1
Clock Source Select register (CLKSRCSEL -
0xE01F C10C) . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2
PLL (Phase Locked Loop) . . . . . . . . . . . . . . . 46
3.2.1
PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2
PLL and startup/boot code interaction . . . . . . 47
3.2.3
PLL register description . . . . . . . . . . . . . . . . . 47
3.2.4
PLL Control register (PLLCON - 0xE01F C080) .
48
3.2.5
PLL Configuration register (PLLCFG -
0xE01F C084) . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.6
PLL Status register (PLLSTAT - 0xE01F C088) . .
51
3.2.7
PLL Interrupt: PLOCK . . . . . . . . . . . . . . . . . . 51
3.2.8
PLL Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.9
PLL Feed register (PLLFEED - 0xE01F C08C) 52
3.2.10
PLL and Power-down mode. . . . . . . . . . . . . . 52
3.2.11
PLL frequency calculation . . . . . . . . . . . . . . . 53
3.2.12
Procedure for determining PLL settings. . . . . 54
3.2.13
Examples of PLL settings . . . . . . . . . . . . . . . 54
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