Renesas HD6417641 用户手册
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 320 of 982
REJ09B0023-0400
12.4.8
Reset Wait Counter (RWTCNT)
RWTCNT is a 7-bit counter. This counter starts to increment by synchronizing the CKIO after a
power-on reset is released, and stops when the value reaches H'007F. External bus access is
suspended while the counter is operating. This counter is provided to minimize the time from
releasing a reset for flash memory to the first access.
power-on reset is released, and stops when the value reaches H'007F. External bus access is
suspended while the counter is operating. This counter is provided to minimize the time from
releasing a reset for flash memory to the first access.
If a value is written to the lower seven bits of this register, the counter starts to increment from the
specified value and the external bus access is suspended until the incrementing has been
completed. When the RWTCNT is written, the upper 16 bits of the write data must be H'A55A to
cancel write protection.
specified value and the external bus access is suspended until the incrementing has been
completed. When the RWTCNT is written, the upper 16 bits of the write data must be H'A55A to
cancel write protection.
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 7
All
0
R
Reserved
These bits are always read as 0.
6 to 0
All 0
R/W
7-Bit Counter