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Section 16   I

2

C Bus Interface 2 (IIC2) 

 

 

Rev. 4.00  Sep. 14, 2005  Page 487 of 982 

 

 REJ09B0023-0400 

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the 
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to 
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during 
transferring data of ICDRS, continuous transfer is possible. 

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR 
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a 
receive-only register, therefore the CPU cannot write to this register. 

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from 
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from 
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the 
CPU. 

NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the 
SCL and SDA pins. For details of the noise filter, see section 16.4.7, Noise Filter. 

NF2CYC is initialized to H'00 by a power-on reset. 

7 to 1 

 All 

0 

R 

Reserved 

These bits are always read as 0. 

0 

NF2CYC  

0 

R/W 

Noise Filtering Range Select 

0: The noise less than one cycle of the peripheral clock 

can be filtered out 

1: The noise less than two cycles of the peripheral clock 

can be filtered out