Renesas HD6417641 用户手册
Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 488 of 982
REJ09B0023-0400
16.4 Operation
The I
2
C bus interface can communicate either in I
2
C bus mode or clocked synchronous serial mode
by setting FS in SAR.
16.4.1 I
2
C Bus Format
Figure 16.3 shows the I
2
C bus formats. Figure 16.4 shows the I
2
C bus timing. The first frame
following a start condition always consists of eight bits.
S
SLA
R/
W
A
DATA
A
A/
A
P
1
1
1
1
n
7
1
m
(a) I
2
C bus format (FS = 0)
(b) I
2
C bus format (Start condition retransmission, FS = 0)
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m
m: Transfer frame count (m
≥ 1)
S
SLA
R/
W
A
DATA
1
1
1
n1
7
1
m1
S
SLA
R/
W
A
DATA
A/
A
P
1
1
1
n2
7
1
m2
1
1
1
A/
A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2
m1 and m2: Transfer frame count (m1 and m2
≥ 1)
1
1
Figure 16.3 I
2
C Bus Formats
SDA
SCL
S
1-7
SLA
8
R/
W
9
A
1-7
DATA
8
9
1-7
8
9
A
DATA
P
A
Figure 16.4 I
2
C Bus Timing