Renesas SH7781 用户手册
24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1179 of 1658
REJ09B0261-0100
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
CMD
START
R
R
R
R
R
R
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 1
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
0
CMDSTART 0
R/W
Starts command transmission when 1 is written. This bit
is automatically cleared to 0 after the MMCIF received
the CMDSTART command. When 0 is written to this bit,
operation is not affected.
is automatically cleared to 0 after the MMCIF received
the CMDSTART command. When 0 is written to this bit,
operation is not affected.
24.3.3
Operation Control Register (OPCR)
OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or
continues data transfer.
continues data transfer.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
DATAEN
RD_
CONTI
CMD
OFF
R
R/W
R/W
R
R
R
R
⎯
⎯
⎯
⎯
⎯
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 CMDOFF
0 R/W
Command
Off
Aborts all command operations (MMCIF command
sequence) when 1 is written after a command is
transmitted. This bit is cleared to 0 automatically after
the MMCIF received the CMDOFF command.
sequence) when 1 is written after a command is
transmitted. This bit is cleared to 0 automatically after
the MMCIF received the CMDOFF command.
Write enabled period: From command transmission
completion to command sequence end
completion to command sequence end
Write of 0: Operation is not affected.
Write of 1: Command sequence is forcibly aborted.
Note: Do not write to this bit out of the write enable
period.