Renesas SH7781 用户手册

29.   User Break Controller (UBC) 

Rev.1.00  Jan. 10, 2008  Page 1468 of 1658 
REJ09B0261-0100 

 

CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the 
break conditions for channel 1.  

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

CD

CD

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit : 

Initial value : 

R/W: 

Bit : 

Initial value : 

R/W: 

 

 

31 to 0 

CD 

Undefined  R/W  Compare Data Value 

Specifies the data value to be included in the break 
conditions.  

When the operand bus has been specified using the 
CBR1 register, specify the SDB data value in CD[31:0]. 

 

Operand bus (byte) 

Don't care 

Don't care 

Don't care 

SDB7 to SDB0 

Operand bus (word) 

Don't care 

Don't care 

SDB15 to SDB8  SDB7 to SDB0 

Operand bus (longword)  SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8  SDB7 to SDB0 

Notes:  1.  If the data value is included in the match conditions, be sure to specify the operand 

size.  

 

2.  The OCBI instruction is handled as longword write access without the data value, and 

the PREF, OCBP, and OCBWB instructions are handled as longword read access 
without the data value. Therefore, do not include the data value in the match conditions 
for these instructions.  

 

3.  If the quadword access is specified and the data value is included in the match 

conditions, the upper and lower 32 bits of 64-bit data are each compared with the 
contents of both the match data setting register and match data mask setting register.