Renesas SH7781 用户手册
29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1469 of 1658
REJ09B0261-0100
29.2.6
Match Data Mask Setting Register 1 (CDMR1)
CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the
data value bits specified using the match data setting register. (Set the bits to be masked to 1.)
data value bits specified using the match data setting register. (Set the bits to be masked to 1.)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CDM
CDM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit :
Initial value :
R/W:
Bit :
Initial value :
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 0
CDM
Undefined R/W
Compare Data Value Mask
Specifies the bits to be masked among the data value
bits specified using the CDR1 register. (Set the bits to
be masked to 1.)
bits specified using the CDR1 register. (Set the bits to
be masked to 1.)
0: Data value bits CD[n] are included in the break
condition.
1: Data value bits CD[n] are masked and not included
in the break condition.
[n] = any values from 31 to 0