Renesas SH7781 用户手册

10.   Interrupt Controller (INTC) 

Rev.1.00  Jan. 10, 2008  Page 325 of 1658 

REJ09B0261-0100 

 

For the IRQ interrupt at level detection, there are the following features according to the setting of 
ICR0.LVLMODE. The initial value of the ICR0 bit in LVLMODE is 0. It is recommended to set 
the bit to 1 before using the INTC. 

= 0 

After an IRQ interrupt request is detected at the level detection, the source is retained in INTREQ 
even if the pin state of IRQ interrupts is changed and the request is turned down before the request 
is accepted by the CPU. The source is retained until the CPU accepts an interrupt (including other 
interrupts), or the correspondence interrupt mask bit is set to 1. 

To clear the IRQ interrupt source retained in the INTC, change the pin state of IRQ interrupts by 
interrupt routine and withdraw the request. Then, clear the source retained in INTREQ to 0. For 
details of clearing, see section 10.7.3, Clearing IRQ and IRL Interrupt Requests. 

= 1 

The INTC does not retain the IRQ interrupt source detected at the level detection. 

The IRL interrupt is an interrupt input as level from pins IRQ/

IRL7 to IRQ/IRL4 or pins 

IRQ/

IRL3 to IRQ/IRL0.  

The priority level is indicated by pins IRQ/

IRL7 to IRQ/IRL4 or pins IRQ/IRL3 to IRQ/IRL0. 

Pins IRQ/

IRL7 to IRQ/IRL4 or pins IRQ/IRL3 to IRQ/IRL0 indicate the interrupt request with the 

highest priority (level 15) when these pins are all low. When these pins are all high, these pins 
indicate no interrupt requests (level 0). Figure 10.3 shows an example of IRL interrupt connection, 
and table 10.12 shows the correspondence between the levels on the IRL pins and interrupt 
priority.