Renesas SH7781 用户手册
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 327 of 1658
REJ09B0261-0100
The priority of IRL interrupts should be retained from when an interrupt is accepted to when
interrupt handling starts. The level can be changed to a higher level.
interrupt handling starts. The level can be changed to a higher level.
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) bit in SR is
automatically set to the level of the accepted interrupt. When the INTMU bit in CPUOPM is
cleared to 0, the IMASK bit in SR is not affected.
automatically set to the level of the accepted interrupt. When the INTMU bit in CPUOPM is
cleared to 0, the IMASK bit in SR is not affected.
When 1 is written to the IRLM0 and IRLM1 bits in ICR0, pins IRQ/
IRL0 to IRQ/IRL3 or
IRQ/
IRL7 to IRQ/IRL4 can be used for independent IRQ interrupts. For details, see section
10.4.2, IRQ Interrupts.
(2)
Dependence on ICR0.LVLMODE Setting
(a)
ICR0.LVLMODE
= 0
After an IRL interrupt request is detected, the IRL interrupt with the highest priority is retained in
the following cases until the CPU accepts an interrupt (including other interrupts). The cases are
where the interrupt request is withdrawn or where the priority is set lower.
the following cases until the CPU accepts an interrupt (including other interrupts). The cases are
where the interrupt request is withdrawn or where the priority is set lower.
To clear the retained IRL interrupt source, change the pin state of IRL interrupts by interrupt
routine and withdraw the interrupt request. The, clear the corresponding interrupt mask bit to 1
(To clear the IRL interrupt request by pins IRQ/
routine and withdraw the interrupt request. The, clear the corresponding interrupt mask bit to 1
(To clear the IRL interrupt request by pins IRQ/
IRL3 to IRQ/IRL0, write 1 to the IM10 bit in
INTMSK1. To clear the IRL interrupt request by pins IRQ/
IRL7 to IRQ/IRL4, write 1 to the IM11
bit in INTMSK1. The IRL interrupt source being detected cannot be cleared even if the masking is
performed in INTMSK2 by the level.).
performed in INTMSK2 by the level.).
(b)
ICR0.LVLMODE
= 1
The INTC does not retain the IRL interrupt source.
10.4.4
On-Chip Peripheral Module Interrupts
On-chip module interrupts are interrupts generated in the on-chip modules.
The interrupt vectors are not allocated to each source, but the source is reflected on INTEVT.
Therefore, the source can be easily identified by branching the value of INTEVT as offset during
exception handling routine.
Therefore, the source can be easily identified by branching the value of INTEVT as offset during
exception handling routine.
A priority ranging from 31 to 0 can be set for each module by INT2PRI0 to INT2PRI9. To notify
the CPU of the priority, round down the least 1-bit and change to 4 bits. For details, see section
10.4.5, Priority of On-Chip Peripheral Module Interrupts.
the CPU of the priority, round down the least 1-bit and change to 4 bits. For details, see section
10.4.5, Priority of On-Chip Peripheral Module Interrupts.