Renesas SH7781 用户手册
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 328 of 1658
REJ09B0261-0100
REJ09B0261-0100
An on-chip peripheral module interrupt source flag or an interrupt enable flag should be updated
when the BL bit in SR is set to 1 or when the corresponding interrupt is not generated by the
setting of interrupt masking occurs. To prevent the acceptance of incorrect interrupts by the
updated interrupt source, read from the on-chip peripheral module register that has the
corresponding flag. Then, clear the BL bit to 0 or update the interrupt masking setting so that the
corresponding interrupt can be accepted, after waiting for the on-chip peripheral module priority
determination time specified by table 10.14, Interrupt Response Time (for example, read from a
register operating with the peripheral module clock in the INTC). These procedures can guarantee
the required timing. To update multiple flag, read from the register that has the last flag after
updating the flag.
when the BL bit in SR is set to 1 or when the corresponding interrupt is not generated by the
setting of interrupt masking occurs. To prevent the acceptance of incorrect interrupts by the
updated interrupt source, read from the on-chip peripheral module register that has the
corresponding flag. Then, clear the BL bit to 0 or update the interrupt masking setting so that the
corresponding interrupt can be accepted, after waiting for the on-chip peripheral module priority
determination time specified by table 10.14, Interrupt Response Time (for example, read from a
register operating with the peripheral module clock in the INTC). These procedures can guarantee
the required timing. To update multiple flag, read from the register that has the last flag after
updating the flag.
If a flag is updated when the BL bit is 0, the processing may skip to interrupt processing routine
with the INTEVT value cleared to 0. This is because interrupt processing starts, relative to the
timing that the flag is updated and the interrupt request is identified in this LSI. The processing
can be continued successfully by executing the RTE instruction.
with the INTEVT value cleared to 0. This is because interrupt processing starts, relative to the
timing that the flag is updated and the interrupt request is identified in this LSI. The processing
can be continued successfully by executing the RTE instruction.
Note that the GPIO interrupt is a low-active interrupts. Unlike the IRL interrupt and the IRQ
interrupt that is detected by the level detection, the GPIO interrupt source cannot be retained by
hardware if the pin state is changed and the interrupt request is withdrawn.
interrupt that is detected by the level detection, the GPIO interrupt source cannot be retained by
hardware if the pin state is changed and the interrupt request is withdrawn.
10.4.5
Priority of On-Chip Peripheral Module Interrupts
When any interrupt is generated, the on-chip peripheral module interrupt outputs the exception
code specific to the source to SH-4A. Accepting the interrupt, Sh-4A indicates the corresponding
INTEVT code in INTEVT. An interrupt handler can identify the source by reading from INTEVT
in SH-4A, without reading the source indicate register in the INTC. For the correspondence
between on-chip peripheral module interrupt sources and exception codes, see table 10.1.
code specific to the source to SH-4A. Accepting the interrupt, Sh-4A indicates the corresponding
INTEVT code in INTEVT. An interrupt handler can identify the source by reading from INTEVT
in SH-4A, without reading the source indicate register in the INTC. For the correspondence
between on-chip peripheral module interrupt sources and exception codes, see table 10.1.
As shown in figure 10.4, an on-chip module interrupt source can be set to 30 levels (H'00 and H'01
mask interrupt requests) by the 5-bit field. The interrupt level receive interface in SH-4A can be
set to 15 levels (H'0 masks interrupt requests) by the 4-bit field. The priority of on-chip peripheral
module interrupts is determined by selecting each interrupt source with 5 bits that are extended 1
bit. Then, change 4 bits that round down the least 1 bit and notifies. For example, two interrupt
sources with priority levels set to H'1A and H'1B will both be output to the CPU as the 4-bit
priority level H'D. The two interrupt sources have the same priority value. However, although the
rounded codes are the same for both interrupt sources, the interrupt with priority level H'1B
clearly has priority when we consider the 5-bit data in the priority setting. That is, the 5-bit values
in the fields give INTC a way to differentiate between interrupts with the same four-bit priority
level. If the interrupts of the same priority coinside, the INTEVT code is notified according to the
priority shown in table 10.13.
mask interrupt requests) by the 5-bit field. The interrupt level receive interface in SH-4A can be
set to 15 levels (H'0 masks interrupt requests) by the 4-bit field. The priority of on-chip peripheral
module interrupts is determined by selecting each interrupt source with 5 bits that are extended 1
bit. Then, change 4 bits that round down the least 1 bit and notifies. For example, two interrupt
sources with priority levels set to H'1A and H'1B will both be output to the CPU as the 4-bit
priority level H'D. The two interrupt sources have the same priority value. However, although the
rounded codes are the same for both interrupt sources, the interrupt with priority level H'1B
clearly has priority when we consider the 5-bit data in the priority setting. That is, the 5-bit values
in the fields give INTC a way to differentiate between interrupts with the same four-bit priority
level. If the interrupts of the same priority coinside, the INTEVT code is notified according to the
priority shown in table 10.13.