Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 486 of 1658
REJ09B0261-0100
REJ09B0261-0100
12.4.4
SDRAM Configuration Setting Register (DBCONF)
The SDRAM configuration setting register (DBCONF) is a readable/writable register. It is
initialized only upon power-on reset.
initialized only upon power-on reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
SPILT0
SPILT1
SPILT2
SPILT3
SPILT4
SPILT5
SPILT6
SPILT7
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BWID
TH0
BWID
TH1
⎯
⎯
⎯
⎯
⎯
⎯
BASFT0
BASFT1
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R
R
R
R
R
R
R/W
R/W
R
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 24
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
guaranteed.
23 to 16 SPLIT7 to
SPLIT0
1001 1010 R/W
Memory Configuration Select Bits
These bits select the memory configuration to be used.
These are used in combination with the BASFT and the
BWIDTH bits. For details on address multiplexing, refer
to section 12.5.6, Regarding Address Multiplexing.
These are used in combination with the BASFT and the
BWIDTH bits. For details on address multiplexing, refer
to section 12.5.6, Regarding Address Multiplexing.
1001 1010: 256-Mbit product (16M
× 16 bits)
1001 1011: 512-Mbit product (32M
× 16 bits)
1101 1011: 1-Gbit product (64M
× 16 bits)
1110 0011: 2-Gbit product (128M
× 16 bits)
0001 1011: 256-Mbit product (32M
× 8 bits)
0010 0011: 512-Mbit product (64M
× 8 bits)
0110 0011: 1-Gbit product (128M
× 8 bits)
0110 1011: 2-Gbit product (256M
× 8 bits)
Other than above: Setting prohibited (If specified,
correct operation cannot be
guaranteed.)
guaranteed.)