Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 488 of 1658
REJ09B0261-0100
REJ09B0261-0100
12.4.5
SDRAM Timing Register 0 (DBTR0)
The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon
power-on reset.
power-on reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
TRAS0
TRAS1
TRAS2
TRAS3
⎯
⎯
⎯
⎯
CL0
CL1
CL2
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R
R
R
R
R
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
TRCD0
TRCD1
TRCD2
⎯
⎯
⎯
⎯
⎯
TRFC0
TRFC1
TRFC2
TRFC3
TRFC4
TRFC5
⎯
TRFC6
R/W
R/W
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 27
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
guaranteed.
26 to 24 CL2 to CL0 010
R/W
CAS Latency Setting Bits
These bits set the CAS latency. These bits should be
set according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
set according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
When using the ODT (On Die Termination) enable
output signal MODT, these bits should be set to 4 or
more cycles.
output signal MODT, these bits should be set to 4 or
more cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
010: 2 cycles
011: 3 cycles
100: 4 cycles
101: 5 cycles
110: 6 cycles
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)