Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 530 of 1658
REJ09B0261-0100
REJ09B0261-0100
12.5.7
Regarding SDRAM Access and Timing Constraints
In this section, waveforms at the various pins during basic DDR2-SDRAM access are explained
first and then the relation between DDR2-SDRAM access and the CAS latency (CL), tRAS, tRFC,
tRCD, tRP, tRRD, tWR, tRTP, tRC, READ-WRITE minimum interval, WRITE-READ minimum
interval set using the SDRAM timing registers 0 to 2 (DBTR0 to DBTR2) is explained.
first and then the relation between DDR2-SDRAM access and the CAS latency (CL), tRAS, tRFC,
tRCD, tRP, tRRD, tWR, tRTP, tRC, READ-WRITE minimum interval, WRITE-READ minimum
interval set using the SDRAM timing registers 0 to 2 (DBTR0 to DBTR2) is explained.
(1)
Basic SDRAM Access
In this section, waveforms at the various pins during basic SDRAM access, including reading,
writing, auto-refresh, and self-refresh operations, are explained.
writing, auto-refresh, and self-refresh operations, are explained.
For the relation between writing and the ODT control signal output, refer to section 12.5.9,
Important Information Regarding ODT Control Signal Output to SDRAM.
Important Information Regarding ODT Control Signal Output to SDRAM.
Figure 12.8 shows waveforms for 1/2/4/8/16-byte reading when the bus width is set to 32 bits. In
this case, single-reading is performed in which the READ command is issued once. In this
example, read access processing is executed for bank A after the ACT command is issued, but
when there is a page hit, access begins with the issue of the READ command.
this case, single-reading is performed in which the READ command is issued once. In this
example, read access processing is executed for bank A after the ACT command is issued, but
when there is a page hit, access begins with the issue of the READ command.