Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 532 of 1658
REJ09B0261-0100
REJ09B0261-0100
MCK0,
MCK1
MCK1
MA[14:11 ]
MA[9:0]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
ACT
bank A
READ
bank A
bank A
Invalid
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0]
Invalid
Invalid
Invalid
SDRAM
command
command
Valid
Invalid
READ
bank A
bank A
Invalid
Invalid
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Valid
Valid
Valid
Valid
Valid
Valid
High level
Example of CL = 3
Read data
Figure 12.9 Waveforms for 32-Byte Reading
(When the Bus Width Is Set to 32 Bits)
Figure 12.10 shows waveforms for 1/2/4/8/16-byte writing when the bus width is set to 32 bits. In
this case, single-writing is performed in which the WRITE command is issued once. In this
example, write access processing is executed for bank A after the ACT command is issued, but
when there is a page hit, access begins with the issue of the WRITE command.
this case, single-writing is performed in which the WRITE command is issued once. In this
example, write access processing is executed for bank A after the ACT command is issued, but
when there is a page hit, access begins with the issue of the WRITE command.