Renesas SH7781 用户手册
16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 768 of 1658
REJ09B0261-0100
REJ09B0261-0100
16.3.5
Watchdog Timer Base Counter (WDTBCNT)
WDTBCNT is a 32-bit read-only register comprising an 18-bit counter that is incremented by the
peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is incremented and WDTBCNT
is cleared to H'0000 0000.
peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is incremented and WDTBCNT
is cleared to H'0000 0000.
WDTBCNT is only reset by a power-on reset. Writing to this register is invalid.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDTBCNT
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
⎯
⎯
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDTBCNT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 18
⎯ All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
17 to 0
WDTBCNT All 0
R
Base counter value