Renesas SH7781 用户手册

16.   Watchdog Timer and Reset (WDT) 

Rev.1.00  Jan. 10, 2008  Page 769 of 1658 

REJ09B0261-0100 

 

Power-on reset and manual reset are available. Their requesting sources are described below. 

•  Requesting sources 

⎯  A low level input on the PRESET pin 
⎯  WDTCNT overflow when the WT/IT bit is 1 and the RSTS bit is 0 in WDTCSR 
⎯  The H-UDI reset (For details, see section 30, User Debugging Interface (H-UDI)) 

 

•  Branch address: H'A000 0000 
•  Operation until branching  

The exception code H'000 is set in EXPEVT. After initializing VBR and SR, the processing 
branches by setting PC = H'A000 0000.  
During initialization, the VBR register is rest to H'0000 0000. The SR register is initialized 
such that the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt 
mask level bits (IMASK3 to IMASK0) are set to B'1111. 
Then, the CPU and peripheral modules are initialized. For details, refer to the register 
descriptions in the corresponding sections.  

At power-on, ensure that a low level is input to the 

PRESET pin. A low level input is also 

needed on the 

TRST pin to initialize the H-UDI. 

 

Power_on_reset() 

{ 

 

 

EXPEVT = H'0000 0000; 

 

 

VBR = H'0000 0000; 

 

 

SR.MD = 1; 

 

 

SR.RB = 1; 

 

 

SR.BL = 1; 

 

 

SR.(I0-I3) = B'1111; 

 

 

SR.FD = 0; 

  Initialize_CPU(); 

  Initialize_Module(PowerOn); 

 

 

PC = H'A000 0000; 

}