Renesas SH7781 用户手册
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 875 of 1658
REJ09B0261-0100
19.3.20
CLAMP Signal Width Register (CLAMPWR)
The CLAMP signal width register (CLAMPWR) sets the high-level width of the CLAMP signal.
The value is retained during power-on reset and manual reset.
The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
Bit:
Initial value:
Bit:
Initial value:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
CLAMPW
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit Bit
Name
Initial
Value R/W
Value R/W
Internal
Update Description
Update Description
31 to 11
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
10 to 0
CLAMPW Undefined R/W
Yes
Clamp Signal Width
The high-level width of the CLAMP signal should
be set in dot clock units.
be set in dot clock units.
If the HSYNC signal falls while the CLAMP
signal is at high level, the CLAMP signal also
falls.
signal is at high level, the CLAMP signal also
falls.