Motorola MCF5281 用户手册

2-28

MOTOROLA

 

The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location
<ea>x shown in this table represent the best-case scenario
when the store instruction is executed and there are no load or
M{S}AC instructions in the EMAC execution pipeline. In
general, these store operations require only a single cycle for
execution, but if preceded immediately  by a load, MAC, or
MSAC instruction, the depth of the EMAC pipeline is exposed
and the execution time is four cycles.

This section describes the new opcodes implemented as part of the Revision A+
enhancements to the basic ColdFire ISA.

bsr

—

—

—

—

3(0/1)

—

—

—

jmp

<ea>

—

3(0/0)

—

—

3(0/0)

4(0/0)

3(0/0)

—

jsr

<ea>

—

3(0/1)

—

—

3(0/1)

4(0/1)

3(0/1)

—

rte

—

—

10(2/0)

—

—

—

—

—

rts

—

—

5(1/0)

—

—

—

—

—

bra

2(0/0)

—

2(0/0)

—

bcc

3(0/0)

1(0/0)

2(0/0)

3(0/0)