用户手册 — Motorola MCF5281

目录

• About This Book

  43
  • Audience

    43
  • Organization

    43
  • Suggested Reading

    46
    • General Information

      46
    • ColdFire Documentation

      46
  • Conventions

    47
  • Acronyms and Abbreviations

    48
  • Terminology Conventions

    49
  • Revision History

    52
• Chapter 1 Overview

  57
  • 1.1 MCF5282 Key Features

    57
    • Figure 1-1. MCF5282 Block Diagram

      63
    • 1.1.1 Version 2 ColdFire Core

      64
      • 1.1.1.1 Cache

        64
        • Table 1-1. Cache Configuration

          64
      • 1.1.1.2 SRAM

        65
      • 1.1.1.3 Flash

        65
      • 1.1.1.4 Debug Module

        65
    • 1.1.2 System Control Module

      66
    • 1.1.3 External Interface Module (EIM)

      66
    • 1.1.4 Chip Select

      67
    • 1.1.5 Power Management

      67
    • 1.1.6 General Input/Output Ports

      67
    • 1.1.7 Interrupt Controllers (INTC0/INTC1)

      67
    • 1.1.8 SDRAM Controller

      67
    • 1.1.9 Test Access Port

      68
    • 1.1.10 UART Modules

      68
    • 1.1.11 DMA Timers (DTIM0-DTIM3)

      69
    • 1.1.12 General-Purpose Timers (GPTA/GPTB)

      69
    • 1.1.13 Periodic Interrupt Timers (PIT0-PIT3)

      69
    • 1.1.14 Software Watchdog Timer

      70
    • 1.1.15 Phase Locked Loop (PLL)

      70
    • 1.1.16 DMA Controller

      70
    • 1.1.17 Reset

      70
  • 1.2 MCF5282-Specific Features

    71
    • 1.2.1 Fast Ethernet Controller (FEC)

      71
    • 1.2.2 FlexCAN

      71
    • 1.2.3 I2C Bus

      71
    • 1.2.4 Queued Serial Peripheral Interface (QSPI)

      71
    • 1.2.5 Queued Analog-to-Digital Converter (QADC)

      71
• Chapter 2 ColdFire Core

  73
  • 2.1 Processor Pipelines

    73
    • Figure 2-1. ColdFire Processor Core Pipelines

      73
  • 2.2 Processor Register Description

    74
    • 2.2.1 User Programming Model

      74
      • 2.2.1.1 Data Registers (D0-D7)

        75
      • 2.2.1.2 Address Registers (A0-A6)

        75
      • 2.2.1.3 Stack Pointer (A7)

        75
      • 2.2.1.4 Program Counter (PC)

        75
        • Figure 2-2. User Programming Model

          76
      • 2.2.1.5 Condition Code Register (CCR)

        76
        • Figure 2-3. Condition Code Register (CCR)

          76
        • Table 2-1. CCR Field Descriptions

          76
    • 2.2.2 EMAC Programming Model

      77
      • Figure 2-4. EMAC Register Set

        77
    • 2.2.3 Supervisor Programming Model

      77
      • Figure 2-5. Supervisor Programming Model

        78
      • 2.2.3.1 Status Register (SR)

        78
        • Figure 2-6. Status Register

          78
        • Table 2-2. SR Field Descriptions (continued)

          78
      • 2.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7)

        79
      • 2.2.3.3 Vector Base Register (VBR)

        80
      • 2.2.3.4 Cache Control Register (CACR)

        80
      • 2.2.3.5 Access Control Registers (ACR0, ACR1)

        80
      • 2.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)

        80
  • 2.3 Programming Model

    80
    • Table 2-3. ColdFire CPU Registers (continued)

      80
  • 2.4 Additions to the Instruction Set Architecture

    81
    • Table 2-4. ISA Revision A+ New Instructions

      82
  • 2.5 Exception Processing Overview

    82
    • Table 2-5. Exception Vector Assignments (continued)

      83
  • 2.6 Exception Stack Frame Definition

    84
    • Figure 2-7. Exception Stack Frame Form

      84
    • Table 2-6. Format Field Encodings

      84
    • Table 2-7. Fault Status Encodings

      85
  • 2.7 Processor Exceptions

    85
    • 2.7.1 Access Error Exception

      85
    • 2.7.2 Address Error Exception

      86
    • 2.7.3 Illegal Instruction Exception

      86
    • 2.7.4 Divide-By-Zero

      86
    • 2.7.5 Privilege Violation

      86
    • 2.7.6 Trace Exception

      86
    • 2.7.7 Unimplemented Line-A Opcode

      87
    • 2.7.8 Unimplemented Line-F Opcode

      87
    • 2.7.9 Debug Interrupt

      87
    • 2.7.10 RTE and Format Error Exception

      88
    • 2.7.11 TRAP Instruction Exception

      88
    • 2.7.12 Interrupt Exception

      88
    • 2.7.13 Fault-on-Fault Halt

      88
    • 2.7.14 Reset Exception

      88
      • Figure 2-8. D0 Hardware Configuration Info

        89
      • Table 2-8. D0 Hardware Configuration Info Field Description

        90
      • Figure 2-9. D1 Hardware Configuration Info

        91
      • Table 2-9. D1 Local Memory Hardware Configuration Information Field Description (continued)

        91
  • 2.8 Instruction Execution Timing

    93
    • 2.8.1 Timing Assumptions

      93
      • Table 2-10. Misaligned Operand References

        94
    • 2.8.2 MOVE Instruction Execution Times

      94
      • Table 2-11. Move Byte and Word Execution Times

        95
      • Table 2-12. Move Long Execution Times

        95
  • 2.9 Standard One Operand Instruction Execution Times

    96
    • Table 2-13. One Operand Instruction Execution Times

      96
  • 2.10 Standard Two Operand Instruction Execution Times

    96
    • Table 2-14. Two Operand Instruction Execution Times (continued)

      96
  • 2.11 Miscellaneous Instruction Execution Times

    98
    • Table 2-15. Miscellaneous Instruction Execution Times

      98
  • 2.12 EMAC Instruction Execution Times

    99
    • Table 2-16. EMAC Instruction Execution Times

      99
  • 2.13 Branch Instruction Execution Times

    100
    • Table 2-17. General Branch Instruction Execution Times

      100
    • Table 2-18. BRA, Bcc Instruction Execution Times

      100
  • 2.14 ColdFire Instruction Set Architecture Enhancements

    100
• Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)

  105
  • 3.1 Multiply-Accumulate Unit

    105
    • Figure 3-1. Multiply-Accumulate Functionality Diagram

      106
  • 3.2 Introduction to the MAC

    106
    • Figure 3-2. Infinite Impulse Response (IIR) Filter

      107
    • Figure 3-3. Four-Tap FIR Filter

      107
  • 3.3 General Operation

    107
    • Figure 3-4. Fractional Alignment

      108
    • Figure 3-5. Signed and Unsigned Integer Alignment

      108
  • 3.4 Memory Map/Register Set

    110
    • Figure 3-6. EMAC Register Set

      110
    • 3.4.1 MAC Status Register (MACSR)

      110
      • Figure 3-7. MAC Status Register (MACSR)

        110
      • Table 3-1. MACSR Field Descriptions (continued)

        111
      • Table 3-2. Summary of S/U, F/I, and R/T Control Bits

        112
      • 3.4.1.1 Fractional Operation Mode

        112
    • 3.4.2 Mask Register (MASK)

      114
  • 3.5 EMAC Instruction Set Summary

    116
    • Table 3-3. EMAC Instruction Summary

      116
    • 3.5.1 EMAC Instruction Execution Times

      116
      • Figure 3-8. EMAC-Specific OEP Sequence Stall

        117
    • 3.5.2 Data Representation

      117
      • Figure 3-9. Two’s Complement, Signed Fractional Equation

        118
    • 3.5.3 MAC Opcodes

      118
• Chapter 4 Cache

  125
  • 4.1 Cache Features

    125
  • 4.2 Cache Physical Organization

    125
    • Figure 4-1. Cache Block Diagram

      127
  • 4.3 Cache Operation

    127
    • 4.3.1 Interaction with Other Modules

      127
    • 4.3.2 Memory Reference Attributes

      128
    • 4.3.3 Cache Coherency and Invalidation

      128
    • 4.3.4 Reset

      129
    • 4.3.5 Cache Miss Fetch Algorithm/Line Fills

      129
      • Table 4-1. Initial Fetch Offset vs. CLNF Bits

        129
      • Table 4-2. Instruction Cache Operation as Defined by CACR[31, 10]

        130
  • 4.4 Cache Programming Model

    131
    • 4.4.1 Cache Registers Memory Map

      131
      • Table 4-3. Memory Map of Cache Registers

        131
    • 4.4.2 Cache Registers

      131
      • 4.4.2.1 Cache Control Register (CACR)

        131
        • Figure 4-2. Cache Control Register (CACR)

          132
        • Table 4-4. CACR Field Descriptions (continued)

          132
        • Table 4-5. Cache Configuration as Defined by CACR[31, 23, 22]

          134
        • Table 4-6. Cache Invalidate All as Defined by CACR[23, 22, 21, 20]

          134
        • Table 4-7. External Fetch Size Based on Miss Address and CLNF

          135
      • 4.4.2.2 Access Control Registers (ACR0, ACR1)

        135
        • Figure 4-3. Access Control Registers (ACR0, ACR1)

          135
        • Table 4-8. ACR Field Descriptions (continued)

          135
• Chapter 5 Static RAM (SRAM)

  137
  • 5.1 SRAM Features

    137
  • 5.2 SRAM Operation

    137
  • 5.3 SRAM Programming Model

    137
    • 5.3.1 SRAM Base Address Register (RAMBAR)

      138
      • Figure 5-1. SRAM Base Address Register (RAMBAR)

        138
      • Table 5-1. SRAM Base Address Register (continued)

        138
    • 5.3.2 SRAM Initialization

      139
    • 5.3.3 SRAM Initialization Code

      140
    • 5.3.4 Power Management

      140
      • Table 5-2. Typical RAMBAR Setting Examples

        140
• Chapter 6 ColdFire Flash Module (CFM)

  143
  • 6.1 Features

    143
  • 6.2 Block Diagram

    144
    • Figure 6-1. CFM Block Diagram

      145
  • 6.3 Memory Map

    146
    • Figure 6-2. CFM Array Memory Map

      146
    • 6.3.1 CFM Configuration Field

      147
      • Table 6-1. CFM Configuration Field

        147
    • 6.3.2 Flash Base Address Register (FLASHBAR)

      147
      • Figure 6-3. Flash Base Address Register (FLASHBAR)

        149
      • Table 6-2. FLASHBAR Field Descriptions

        149
    • 6.3.3 CFM Registers

      150
      • Table 6-3. CFM Register Address Map

        150
    • 6.3.4 Register Descriptions

      150
      • 6.3.4.1 CFM Configuration Register (CFMCR)

        150
        • Figure 6-4. CFM Module Configuration Register (CFMCR)

          150
        • Table 6-4. CFMCR Field Descriptions

          151
      • 6.3.4.2 CFM Clock Divider Register (CFMCLKD)

        151
        • Figure 6-5. CFM Clock Divider Register (CFMCLKD)

          151
        • Table 6-5. CFMCLKD Field Descriptions

          152
      • 6.3.4.3 CFM Security Register (CFMSEC)

        152
        • Figure 6-6. CFM Security Register (CFMSEC)

          152
        • Table 6-6. CFMSEC Field Descriptions

          153
      • 6.3.4.4 CFM Protection Register (CFMPROT)

        154
        • Figure 6-7. CFM Protection Register (CFMPROT)

          154
        • Table 6-7. CFMPROT Field Descriptions

          154
        • Figure 6-8. CFMPROT Protection Diagram

          155
      • 6.3.4.5 CFM Supervisor Access Register (CFMSACC)

        155
        • Figure 6-9. CFM Supervisor Access Register (CFMSACC)

          155
        • Table 6-8. CFMSACC Field Descriptions

          156
      • 6.3.4.6 CFM Data Access Register (CFMDACC)

        156
        • Figure 6-10. CFM Data Access Register (CFMDACC)

          156
        • Table 6-9. CFMDACC Field Descriptions

          156
      • 6.3.4.7 CFM User Status Register (CFMUSTAT)

        157
        • Figure 6-11. CFM User Status Register (CFMUSTAT)

          157
        • Table 6-10. CFMUSTAT Field Descriptions

          157
      • 6.3.4.8 CFM Command Register (CFMCMD)

        158
        • Figure 6-12. CFM Command Register (CFMCMD)

          158
        • Table 6-11. CFMCMD Field Descriptions

          158
        • Table 6-12. CFMCMD User Mode Commands

          158
  • 6.4 CFM Operation

    159
    • 6.4.1 Read Operations

      159
    • 6.4.2 Write Operations

      159
    • 6.4.3 Program and Erase Operations

      159
      • 6.4.3.1 Setting the CFMCLKD Register

        160
      • 6.4.3.2 Program, Erase, and Verify Sequences

        161
      • 6.4.3.3 Flash Valid Commands

        162
        • Table 6-13. Flash User Commands

          162
        • Figure 6-13. Example Program Algorithm

          163
      • 6.4.3.4 Flash User Mode Illegal Operations

        164
    • 6.4.4 Stop Mode

      164
    • 6.4.5 Master Mode

      165
  • 6.5 Flash Security Operation

    165
    • 6.5.1 Back Door Access

      166
    • 6.5.2 Erase Verify Check

      166
  • 6.6 Reset

    166
  • 6.7 Interrupts

    167
    • Table 6-14. CFM Interrupt Sources

      167
• Chapter 7 Power Management

  169
  • 7.1 Features

    169
  • 7.2 Memory Map and Registers

    169
    • 7.2.1 Programming Model

      169
    • 7.2.2 Memory Map

      170
      • Table 7-1. Chip Configuration Module Memory Map

        170
    • 7.2.3 Register Descriptions

      170
      • 7.2.3.1 Low-Power Interrupt Control Register (LPICR)

        170
        • Figure 7-1. Low-Power Interrupt Control Register (LPICR)

          171
        • Table 7-2. LPICR Field Description

          171
        • Table 7-3. XLPM_IPL Settings

          172
      • 7.2.3.2 Low-Power Control Register (LPCR)

        172
        • Figure 7-2. Low-Power Control Register (LPCR)

          172
        • Table 7-4. LPCR Field Descriptions

          172
        • Table 7-5. Low-Power Modes

          173
        • Table 7-6. PLL/CLKOUT Stop Mode Operation

          173
  • 7.3 Functional Description

    173
    • 7.3.1 Low-Power Modes

      173
      • 7.3.1.1 Run Mode

        174
      • 7.3.1.2 Wait Mode

        174
      • 7.3.1.3 Doze Mode

        174
      • 7.3.1.4 Stop Mode

        174
      • 7.3.1.5 Peripheral Shut Down

        175
    • 7.3.2 Peripheral Behavior in Low-Power Modes

      175
      • 7.3.2.1 ColdFire Core

        175
      • 7.3.2.2 Static Random-Access Memory (SRAM)

        175
      • 7.3.2.3 Flash

        175
      • 7.3.2.4 System Control Module (SCM)

        175
      • 7.3.2.5 SDRAM Controller (SDRAMC)

        176
      • 7.3.2.6 Chip Select Module

        176
      • 7.3.2.7 DMA Controller (DMAC0-DMA3)

        176
      • 7.3.2.8 UART Modules (UART0, UART1, and UART2)

        176
      • 7.3.2.9 I2C Module

        177
      • 7.3.2.10 Queued Serial Peripheral Interface (QSPI)

        177
      • 7.3.2.11 DMA Timers (DMAT0-DMAT3)

        177
      • 7.3.2.12 Interrupt Controllers (INTC0, INTC1)

        178
      • 7.3.2.13 Fast Ethernet Controller (FEC)

        178
      • 7.3.2.14 I/O Ports

        178
      • 7.3.2.15 Reset Controller

        178
      • 7.3.2.16 Chip Configuration Module

        179
      • 7.3.2.17 Clock Module

        179
      • 7.3.2.18 Edge Port

        180
      • 7.3.2.19 Watchdog Timer

        180
      • 7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)

        180
      • 7.3.2.21 Queued Analog-to-Digital Converter (QADC)

        180
      • 7.3.2.22 General Purpose Timers (GPTA and GPTB)

        181
      • 7.3.2.23 FlexCAN

        181
      • 7.3.2.24 ColdFire Flash Module

        183
      • 7.3.2.25 BDM

        184
      • 7.3.2.26 JTAG

        184
    • 7.3.3 Summary of Peripheral State During Low-Power Modes

      184
      • Table 7-7. CPU and Peripherals in Low-Power Modes (continued)

        184
• Chapter 8 System Control Module (SCM)

  187
  • 8.1 Overview

    187
  • 8.2 Features

    187
  • 8.3 Memory Map and Register Definition

    188
    • Table 8-1. SCM Register Map

      188
  • 8.4 Register Descriptions

    189
    • 8.4.1 Internal Peripheral System Base Address Register (IPSBAR)

      189
      • Figure 8-1. IPS Base Address Register (IPSBAR)

        190
      • Table 8-2. IPSBAR Field Description

        190
    • 8.4.2 Memory Base Address Register (RAMBAR)

      190
      • Figure 8-2. Memory Base Address Register (RAMBAR)

        191
      • Table 8-3. RAMBAR Field Description

        191
    • 8.4.3 Core Reset Status Register (CRSR)

      192
      • Figure 8-3. Core Reset Status Register (CRSR)

        192
      • Table 8-4. CRSR Field Descriptions

        192
    • 8.4.4 Core Watchdog Control Register (CWCR)

      192
      • Figure 8-4. Core Watchdog Control Register (CWCR)

        194
      • Table 8-5. CWCR Field Description

        194
      • Table 8-6. Core Watchdog Timer Delay

        194
    • 8.4.5 Core Watchdog Service Register (CWSR)

      195
      • Figure 8-5. Core Watchdog Service Register (CWSR)

        195
  • 8.5 Internal Bus Arbitration

    195
    • Figure 8-6. Arbiter Module Functions

      196
    • 8.5.1 Overview

      197
    • 8.5.2 Arbitration Algorithms

      197
      • 8.5.2.1 Round-Robin Mode

        197
      • 8.5.2.2 Fixed Mode

        198
    • 8.5.3 Bus Master Park Register (MPARK)

      198
      • Figure 8-7. Default Bus Master Park Register (MPARK)

        198
      • Table 8-7. MPARK Field Description

        199
  • 8.6 System Access Control Unit (SACU)

    200
    • 8.6.1 Overview

      200
    • 8.6.2 Features

      200
    • 8.6.3 Memory Map/Register Definition

      201
      • Table 8-8. SACU Register Memory Map (continued)

        201
      • 8.6.3.1 Master Privilege Register (MPR)

        202
        • Figure 8-8. Master Privilege Register (MPR)

          202
        • Table 8-9. MPR[n] Field Descriptions

          202
      • 8.6.3.2 Peripheral Access Control Registers (PACR 0-PACR8)

        202
        • Figure 8-9. Peripheral Access Control Register (PACRn)

          203
        • Table 8-10. PACR Field Descriptions

          203
        • Table 8-11. PACR ACCESSCTRL Bit Encodings

          203
        • Table 8-12. Peripheral Access Control Registers (PACRs) (continued)

          203
      • 8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 and GPACR1)

        204
        • Figure 8-10. GPACR Register

          204
        • Table 8-13. Grouped PeripheralAccess Control Register (GPACR) Field Descriptions

          205
        • Table 8-14. GPACR ACCESS_CTRL Bit Encodings

          205
        • Table 8-15. GPACR Address Space

          206
• Chapter 9 Clock Module

  207
  • 9.1 Features

    207
  • 9.2 Modes of Operation

    207
    • 9.2.1 Normal PLL Mode

      207
    • 9.2.2 1:1 PLL Mode

      208
    • 9.2.3 External Clock Mode

      208
  • 9.3 Low-power Mode Operation

    208
    • Table 9-1. Clock Module Operation in Low-power Modes

      208
  • 9.4 Block Diagram

    209
    • Figure 9-1. Clock Module Block Diagram

      209
    • Figure 9-2. PLL Block Diagram

      210
  • 9.5 Signal Descriptions

    210
    • Table 9-2. Signal Properties

      210
    • 9.5.1 EXTAL

      210
    • 9.5.2 XTAL

      211
    • 9.5.3 CLKOUT

      211
    • 9.5.4 CLKMOD[1:0]

      211
    • 9.5.5 RSTOUT

      211
  • 9.6 Memory Map and Registers

    211
    • 9.6.1 Module Memory Map

      211
      • Table 9-3. Clock Module Memory Map

        211
    • 9.6.2 Register Descriptions

      212
      • 9.6.2.1 Synthesizer Control Register (SYNCR)

        212
        • Figure 9-3. Synthesizer Control Register (SYNCR)

          212
        • Table 9-4. SYNCR Field Descriptions (continued)

          212
      • 9.6.2.2 Synthesizer Status Register (SYNSR)

        214
        • Figure 9-4. Synthesizer Status Register (SYNSR)

          214
        • Table 9-5. SYNSR Field Descriptions (continued)

          215
        • Table 9-6. System Clock Modes

          216
  • 9.7 Functional Description

    216
    • 9.7.1 System Clock Modes

      216
      • Table 9-7. Clock Out and Clock In Relationships

        217
    • 9.7.2 Clock Operation During Reset

      217
    • 9.7.3 System Clock Generation

      217
    • 9.7.4 PLL Operation

      218
      • Figure 9-5. Crystal Oscillator Example

        218
      • 9.7.4.1 Phase and Frequency Detector (PFD)

        218
      • 9.7.4.2 Charge Pump/Loop Filter

        219
        • Table 9-8. Charge Pump Current and MFD in Normal Mode Operation

          219
      • 9.7.4.3 Voltage Control Output (VCO)

        219
      • 9.7.4.4 Multiplication Factor Divider (MFD)

        219
      • 9.7.4.5 PLL Lock Detection

        220
        • Figure 9-6. Lock Detect Sequence

          221
      • 9.7.4.6 PLL Loss of Lock Conditions

        221
      • 9.7.4.7 PLL Loss of Lock Reset

        221
      • 9.7.4.8 Loss of Clock Detection

        222
      • 9.7.4.9 Loss of Clock Reset

        222
      • 9.7.4.10 Alternate Clock Selection

        222
        • Table 9-9. Loss of Clock Summary

          222
      • 9.7.4.11 Loss of Clock in Stop Mode

        223
        • Table 9-10. Stop Mode Operation (Sheet 5 of 5)

          223
• Chapter 10 Interrupt Controller Modules

  229
  • 10.1 68K/ColdFire Interrupt Architecture Overview

    229
    • 10.1.1 Interrupt Controller Theory of Operation

      231
      • Table 10-1. Interrupt Priority Within a Level

        231
      • 10.1.1.1 Interrupt Recognition

        231
      • 10.1.1.2 Interrupt Prioritization

        231
      • 10.1.1.3 Interrupt Vector Determination

        232
  • 10.2 Memory Map

    233
    • Table 10-2. Interrupt Controller Base Addresses

      233
    • Table 10-3. Interrupt Controller Memory Map (continued)

      233
  • 10.3 Register Descriptions

    234
    • 10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)

      234
      • Figure 10-1. Interrupt Pending Register High (IPRHn)

        235
      • Table 10-4. IPRHn Field Descriptions

        235
      • Figure 10-2. Interrupt Pending Register Low (IPRLn)

        235
      • Table 10-5. IPRLn Field Descriptions

        235
    • 10.3.2 Interrupt Mask Register (IMRHn, IMRLn)

      236
      • Figure 10-3. Interrupt Mask Register High (IMRHn)

        236
      • Table 10-6. IMRHn Field Descriptions

        236
      • Figure 10-4. Interrupt Mask Register Low (IMRLn)

        236
      • Table 10-7. IMRLn Field Descriptions

        237
    • 10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)

      237
      • Figure 10-5. Interrupt Force Register High (INTFRCHn)

        237
      • Table 10-8. INTFRCHn Field Descriptions

        237
      • Figure 10-6. Interrupt Force Register Low (INTFRCLn)

        238
      • Table 10-9. INTFRCLn Field Descriptions

        238
    • 10.3.4 Interrupt Request Level Register (IRLRn)

      238
      • Figure 10-7. Interrupt RequestLevel Register (IRLRn)

        238
      • Table 10-10. IRQn Field Descriptions

        238
    • 10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)

      239
      • Figure 10-8. IACK Level and Priority Register (IACKLPRn)

        239
      • Table 10-11. IACKLPRn Field Descriptions

        239
    • 10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))

      239
      • Figure 10-9. Interrupt Control Register (ICRnx)

        240
      • Table 10-12. ICRnx Field Descriptions

        240
      • 10.3.6.1 Interrupt Sources

        240
        • Table 10-13. Interrupt Source Assignment for INTC0 (continued)

          240
        • Table 10-14. Interrupt Source Assignment for INTC1

          243
    • 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)

      243
      • Figure 10-10. Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)

        244
      • Table 10-15. SWIACK and L1IACK-L7IACK Field Descriptions

        244
  • 10.4 Prioritization Between Interrupt Controllers

    244
  • 10.5 Low-Power Wakeup Operation

    245
• Chapter 11 Edge Port Module (EPORT)

  247
  • 11.1 Introduction

    247
    • Figure 11-1. EPORT Block Diagram

      247
  • 11.2 Low-Power Mode Operation

    247
    • Table 11-1. Edge Port Module Operation in Low-power Modes

      248
  • 11.3 Interrupt/General-Purpose I/O Pin Descriptions

    248
  • 11.4 Memory Map and Registers

    249
    • 11.4.1 Memory Map

      249
      • Table 11-2. Edge Port Module Memory Map

        249
    • 11.4.2 Registers

      249
      • 11.4.2.1 EPORT Pin Assignment Register (EPPAR)

        250
        • Figure 11-2. EPORT Pin Assignment Register (EPPAR)

          250
        • Table 11-3. EPPAR Field Descriptions

          250
      • 11.4.2.2 EPORT Data Direction Register (EPDDR)

        250
        • Figure 11-3. EPORT Data Direction Register (EPDDR)

          250
        • Table 11-4. EPDD Field Descriptions

          251
      • 11.4.2.3 Edge Port Interrupt Enable Register (EPIER)

        251
        • Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)

          251
        • Table 11-5. EPIER Field Descriptions

          251
      • 11.4.2.4 Edge Port Data Register (EPDR)

        251
        • Figure 11-5. EPORT Port Data Register (EPDR)

          251
        • Table 11-6. EPDR Field Descriptions

          252
      • 11.4.2.5 Edge Port Pin Data Register (EPPDR)

        252
        • Figure 11-6. EPORT Port Pin Data Register (EPPDR)

          252
        • Table 11-7. EPPDR Field Descriptions

          252
      • 11.4.2.6 Edge Port Flag Register (EPFR)

        252
        • Figure 11-7. EPORT Port Flag Register (EPFR)

          252
        • Table 11-8. EPFR Field Descriptions

          253
• Chapter 12 Chip Select Module

  255
  • 12.1 Overview

    255
  • 12.2 Chip Select Module Signals

    255
    • Table 12-1. Chip Select Module Signals

      255
    • Table 12-2. Byte Enables/Byte Write Enable Signal Settings

      256
  • 12.3 Chip Select Operation

    257
    • 12.3.1 General Chip Select Operation

      257
      • Table 12-3. Accesses by Matches in CSARs and DACRs

        258
      • 12.3.1.1 8-, 16-, and 32-Bit Port Sizing

        258
        • Figure 12-1. Connections for External Memory Port Sizes

          258
      • 12.3.1.2 External Boot Chip Select Operation

        258
        • Table 12-4. D[19:18] External Boot Chip Select Configuration

          259
  • 12.4 Chip Select Registers

    259
    • Table 12-5. Chip Select Registers (continued)

      259
    • 12.4.1 Chip Select Module Registers

      260
      • 12.4.1.1 Chip Select Address Registers (CSAR0-CSAR6)

        260
        • Figure 12-2. Chip Select Address Registers (CSARn)

          260
        • Table 12-6. CSARn Field Description

          261
      • 12.4.1.2 Chip Select Mask Registers (CSMR0-CSMR6)

        261
        • Figure 12-3. Chip Select Mask Registers (CSMRn)

          261
        • Table 12-7. CSMRn Field Descriptions (continued)

          261
      • 12.4.1.3 Chip Select Control Registers (CSCR0-CSCR6)

        262
        • Figure 12-4. Chip Select Control Registers (CSCRn)

          262
        • Table 12-8. CSCRn Field Descriptions

          263
• Chapter 13 External Interface Module (EIM)

  265
  • 13.1 Features

    265
  • 13.2 Bus and Control Signals

    265
    • Table 13-1. ColdFire Bus Signal Summary (Continued)

      265
  • 13.3 Bus Characteristics

    266
    • Figure 13-1. Signal Relationship to CLKOUT for Non-DRAM Access

      266
  • 13.4 Data Transfer Operation

    266
    • Figure 13-2. Connections for External Memory Port Sizes

      267
    • Figure 13-3. Chip-Select Module Output Timing Diagram

      267
    • 13.4.1 Bus Cycle Execution

      267
      • Table 13-2. Accesses by Matches in CSCRs and DACRs

        268
    • 13.4.2 Data Transfer Cycle States

      269
      • Figure 13-4. Data Transfer State Transition Diagram

        269
      • Table 13-3. Bus Cycle States (Continued)

        269
    • 13.4.3 Read Cycle

      270
      • Figure 13-5. Read Cycle Flowchart

        271
      • Figure 13-6. Basic Read Bus Cycle

        271
    • 13.4.4 Write Cycle

      272
      • Figure 13-7. Write Cycle Flowchart

        272
      • Figure 13-8. Basic Write Bus Cycle

        272
    • 13.4.5 Fast Termination Cycles

      273
      • Figure 13-9. Read Cycle with Fast Termination

        273
      • Figure 13-10. Write Cycle with Fast Termination

        273
    • 13.4.6 Back-to-Back Bus Cycles

      274
      • Figure 13-11. Back-to-Back Bus Cycles

        274
    • 13.4.7 Burst Cycles

      274
      • 13.4.7.1 Line Transfers

        275
        • Table 13-4. Allowable Line Access Patterns

          275
      • 13.4.7.2 Line Read Bus Cycles

        275
        • Figure 13-12. Line Read Burst (2-1-1-1), External Termination

          275
        • Figure 13-13. Line Read Burst (2-1-1-1), Internal Termination

          276
        • Figure 13-14. Line Read Burst (3-2-2-2), External Termination

          276
        • Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination

          277
      • 13.4.7.3 Line Write Bus Cycles

        277
        • Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination

          277
        • Figure 13-17. Line Write Burst (3-2-2-2) with One Wait State

          278
        • Figure 13-18. Line Write Burst-Inhibited

          278
  • 13.5 Misaligned Operands

    278
    • Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)

      279
    • Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)

      279
• Chapter 14 Signal Descriptions

  281
  • 14.1 Overview

    281
    • Figure 14-1. MCF5282 Block Diagram with Signal Interfaces

      282
    • Table 14-1. MCF5282 Signal Description (Continued)

      283
    • Table 14-2. MCF5282 Alphabetical Signal Index (Continued)

      288
    • Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (Continued)

      291
    • 14.1.1 Single-Chip Mode

      296
      • Table 14-4. Pin Reset States at Reset (Single-Chip Mode)

        297
    • 14.1.2 External Boot Mode

      297
      • Table 14-5. Default Signal Functions After System Reset (External Boot Mode) (Continued)

        297
  • 14.2 MCF5282 External Signals

    298
    • 14.2.1 External Interface Module (EIM) Signals

      298
      • 14.2.1.1 Address Bus (A[23:0])

        298
      • 14.2.1.2 Data Bus (D[31:0])

        298
      • 14.2.1.3 Byte Strobes (BS[3:0])

        298
      • 14.2.1.4 Output Enable (OE)

        299
      • 14.2.1.5 Transfer Acknowledge (TA)

        299
      • 14.2.1.6 Transfer Error Acknowledge (TEA)

        299
      • 14.2.1.7 Read/Write (R/W)

        299
      • 14.2.1.8 Transfer Size(SIZ[1:0])

        299
        • Table 14-6. Transfer Size Encoding

          300
      • 14.2.1.9 Transfer Start (TS)

        300
      • 14.2.1.10 Transfer In Progress (TIP)

        300
      • 14.2.1.11 Chip Selects (CS[6:0])

        300
    • 14.2.2 SDRAM Controller Signals

      301
      • 14.2.2.1 SDRAM Row Address Strobe (SRAS)

        301
      • 14.2.2.2 SDRAM Column Address Strobe (SCAS)

        301
      • 14.2.2.3 SDRAM Write Enable (DRAMW)

        301
      • 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])

        301
      • 14.2.2.5 SDRAM Clock Enable (SCKE)

        301
    • 14.2.3 Clock and Reset Signals

      302
      • 14.2.3.1 Reset In (RSTI)

        302
      • 14.2.3.2 Reset Out (RSTO)

        302
      • 14.2.3.3 EXTAL

        302
      • 14.2.3.4 XTAL

        302
      • 14.2.3.5 Clock Output (CLKOUT)

        302
    • 14.2.4 Chip Configuration Signals

      302
      • 14.2.4.1 RCON

        302
      • 14.2.4.2 CLKMOD[1:0]

        302
    • 14.2.5 External Interrupt Signals

      303
      • 14.2.5.1 External Interrupts (IRQ[7:1])

        303
    • 14.2.6 Ethernet Module Signals

      303
      • 14.2.6.1 Management Data (EMDIO)

        303
      • 14.2.6.2 Management Data Clock (EMDC)

        303
      • 14.2.6.3 Transmit Clock (ETXCLK)

        303
      • 14.2.6.4 Transmit Enable (ETXEN)

        303
      • 14.2.6.5 Transmit Data 0 (ETXD0)

        303
      • 14.2.6.6 Collision (ECOL)

        304
      • 14.2.6.7 Receive Clock (ERXCLK)

        304
      • 14.2.6.8 Receive Data Valid (ERXDV)

        304
      • 14.2.6.9 Receive Data 0 (ERXD0)

        304
      • 14.2.6.10 Carrier Receive Sense (ECRS)

        304
      • 14.2.6.11 Transmit Data 1-3 (ETXD[3:1])

        304
      • 14.2.6.12 Transmit Error (ETXER)

        304
      • 14.2.6.13 Receive Data 1-3 (ERXD[3:1])

        305
      • 14.2.6.14 Receive Error (ERXER)

        305
    • 14.2.7 Queued Serial Peripheral Interface (QSPI) Signals

      305
      • 14.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT)

        305
      • 14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN)

        305
      • 14.2.7.3 QSPI Serial Clock (QSPI_CLK)

        305
      • 14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0])

        305
    • 14.2.8 FlexCAN Signals

      306
      • 14.2.8.1 FlexCAN Transmit (CANTX)

        306
      • 14.2.8.2 FlexCAN Receive (CANRX)

        306
    • 14.2.9 I2C Signals

      306
      • 14.2.9.1 Serial Clock (SCL)

        306
      • 14.2.9.2 Serial Data (SDA)

        306
    • 14.2.10 UART Module Signals

      306
      • 14.2.10.1 Transmit Serial Data Output (UTXD[2:0])

        306
      • 14.2.10.2 Receive Serial Data Input (URXD[2:0])

        307
      • 14.2.10.3 Clear-to-Send (UCTS[1:0])

        307
      • 14.2.10.4 Request-to-Send (URTS[1:0])

        307
    • 14.2.11 General Purpose Timer Signals

      307
      • 14.2.11.1 GPTA[3:0]

        307
      • 14.2.11.2 GPTB[3:0]

        307
      • 14.2.11.3 External Clock Input (SYNCA/SYNCB)

        307
    • 14.2.12 DMA Timer Signals

      308
      • 14.2.12.1 DMA Timer 0 Input (DTIN0)

        308
      • 14.2.12.2 DMA Timer 0 Output (DTOUT0)

        308
      • 14.2.12.3 DMA Timer 1 Input (DTIN1)

        308
      • 14.2.12.4 DMA Timer 1 Output (DTOUT1)

        308
      • 14.2.12.5 DMA Timer 2 Input (DTIN2)

        308
      • 14.2.12.6 DMA Timer 2 Output (DTOUT2)

        308
      • 14.2.12.7 DMA Timer 3 Input (DTIN3)

        309
      • 14.2.12.8 DMA Timer 3 Output (DTOUT3)

        309
    • 14.2.13 Analog-to-Digital Converter Signals

      309
      • 14.2.13.1 QADC Analog Input (AN0/ANW)

        309
      • 14.2.13.2 QADC Analog Input (AN1/ANX)

        309
      • 14.2.13.3 QADC Analog Input (AN2/ANY)

        309
      • 14.2.13.4 QADC Analog Input (AN3/ANZ)

        309
      • 14.2.13.5 QADC Analog Input (AN52/MA0)

        309
      • 14.2.13.6 QADC Analog Input (AN53/MA1)

        310
      • 14.2.13.7 QADC Analog Input (AN55/TRIG1)

        310
      • 14.2.13.8 QADC Analog Input (AN56/TRIG2)

        310
    • 14.2.14 Debug Support Signals

      310
      • 14.2.14.1 JTAG_EN

        310
      • 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)

        310
      • 14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS)

        311
      • 14.2.14.4 Development Serial Input/Test Data (DSI/TDI)

        311
      • 14.2.14.5 Development Serial Output/Test Data (DSO/TDO)

        311
      • 14.2.14.6 Test Clock (TCLK)

        311
      • 14.2.14.7 Debug Data (DDATA[3:0])

        312
      • 14.2.14.8 Processor Status Outputs (PST[3:0])

        312
        • Table 14-7. Processor Status Encoding

          312
    • 14.2.15 Test Signals

      312
      • 14.2.15.1 Test (TEST)

        312
    • 14.2.16 Power and Reference Signals

      313
      • 14.2.16.1 QADC Analog Reference (VRH, VRL)

        313
      • 14.2.16.2 QADC Analog Supply (VDDA, VSSA)

        313
      • 14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL)

        313
      • 14.2.16.4 QADC Positive Supply (VDDH)

        313
      • 14.2.16.5 Power for Flash Erase/Program (VPP)

        313
      • 14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF)

        313
      • 14.2.16.7 Standby Power (VSTBY)

        313
      • 14.2.16.8 Positive Supply (VDD)

        313
      • 14.2.16.9 Ground (VSS)

        313
• Chapter 15 Synchronous DRAM Controller Module

  315
  • 15.1 Overview

    315
    • 15.1.1 Definitions

      315
    • 15.1.2 Block Diagram and Major Components

      316
      • Figure 15-1. Synchronous DRAM Controller Block Diagram

        316
  • 15.2 SDRAM Controller Operation

    317
    • Table 15-1. SDRAM Commands

      317
    • 15.2.1 DRAM Controller Signals

      318
      • Table 15-2. Synchronous DRAM Signal Connections

        318
    • 15.2.2 Memory Map for SDRAMC Registers

      318
      • Table 15-3. DRAM Controller Registers

        318
      • 15.2.2.1 DRAM Control Register (DCR)

        319
        • Figure 15-2. DRAM Control Register (DCR)

          319
        • Table 15-4. DCR Field Descriptions

          319
      • 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)

        320
        • Figure 15-3. DRAM Address and Control Register (DACRn)

          320
        • Table 15-5. DACRn Field Descriptions (continued)

          320
      • 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)

        322
        • Figure 15-4. DRAM Controller Mask Registers (DMRn)

          322
        • Table 15-6. DMRn Field Descriptions

          322
    • 15.2.3 General Synchronous Operation Guidelines

      323
      • 15.2.3.1 Address Multiplexing

        323
        • Table 15-7. Generic Address Multiplexing Scheme

          323
        • Table 15-8. MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)

          324
        • Table 15-9. MCF5282 to SDRAM Interface (8-Bit Port,10-Column Address Lines)

          324
        • Table 15-10. MCF5282 to SDRAM Interface (8-Bit Port,11-Column Address Lines)

          324
        • Table 15-11. MCF5282 to SDRAM Interface (8-Bit Port,12-Column Address Lines)

          324
        • Table 15-12. MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)

          324
        • Table 15-13. MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)

          325
        • Table 15-14. MCF5282 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)

          325
        • Table 15-15. MCF5282 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)

          325
        • Table 15-16. MCF5282 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)

          325
        • Table 15-17. MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)

          325
        • Table 15-18. MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)

          326
        • Table 15-19. MCF5282 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)

          326
        • Table 15-20. MCF5282 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)

          326
        • Table 15-21. MCF5282 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)

          326
        • Table 15-22. MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)

          326
        • Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)

          327
      • 15.2.3.2 SDRAM Byte Strobe Connections

        327
        • Figure 15-5. Connections for External Memory Port Sizes

          327
      • 15.2.3.3 Interfacing Example

        327
        • Table 15-24. SDRAM Hardware Connections

          327
      • 15.2.3.4 Burst Page Mode

        327
        • Figure 15-6. Burst Read SDRAM Access

          328
        • Figure 15-7. Burst Write SDRAM Access

          329
      • 15.2.3.5 Auto-Refresh Operation

        329
        • Figure 15-8. Auto-Refresh Operation

          330
      • 15.2.3.6 Self-Refresh Operation

        330
        • Figure 15-9. Self-Refresh Operation

          331
    • 15.2.4 Initialization Sequence

      331
      • 15.2.4.1 Mode Register Settings

        332
        • Figure 15-10. Mode Register Set (mrs) Command

          333
  • 15.3 SDRAM Example

    333
    • Table 15-25. SDRAM Example Specifications

      333
    • 15.3.1 SDRAM Interface Configuration

      334
      • Table 15-26. SDRAM Hardware Connections

        334
    • 15.3.2 DCR Initialization

      334
      • Figure 15-11. Initialization Values for DCR

        334
      • Table 15-27. DCR Initialization Values

        334
    • 15.3.3 DACR Initialization

      334
      • Figure 15-12. SDRAM Configuration

        335
      • Figure 15-13. DACR Register Configuration

        335
      • Table 15-28. DACR Initialization Values (continued)

        335
    • 15.3.4 DMR Initialization

      336
      • Figure 15-14. DMR0 Register

        336
      • Table 15-29. DMR0 Initialization Values (continued)

        336
    • 15.3.5 Mode Register Initialization

      337
      • Table 15-30. Mode Register Initialization

        337
      • Table 15-31. Mode Register Mapping to MCF5282 A[31:0]

        337
    • 15.3.6 Initialization Code

      338
• Chapter 16 DMA Controller Module

  341
  • 16.1 Overview

    341
    • Figure 16-1. DMA Signal Diagram

      342
    • 16.1.1 DMA Module Features

      342
  • 16.2 DMA Request Control (DMAREQC)

    343
    • Figure 16-2. DMA Request Control Register (DMAREQC)

      343
    • Table 16-1. DMAREQC Field Description

      343
  • 16.3 DMA Transfer Overview

    344
    • Figure 16-3. Dual-Address Transfer

      344
  • 16.4 DMA Controller Module Programming Model

    345
    • Table 16-2. Memory Map for DMA Controller Module Registers

      345
    • 16.4.1 Source Address Registers (SAR0-SAR3)

      346
      • Figure 16-4. Source Address Registers (SARn)

        346
    • 16.4.2 Destination Address Registers (DAR0-DAR3)

      346
      • Figure 16-5. Destination Address Registers (DARn)

        346
    • 16.4.3 Byte Count Registers (BCR0-BCR3)

      347
      • Figure 16-6. Byte Count Registers (BCRn)-BCR24BIT = 1

        347
      • Figure 16-7. Byte Count Registers (BCRn)-BCR24BIT = 0

        347
    • 16.4.4 DMA Control Registers (DCR0-DCR3)

      348
      • Figure 16-8. DMA Control Registers (DCRn)

        348
      • Table 16-3. DCRn Field Descriptions (continued)

        348
    • 16.4.5 DMA Status Registers (DSR0-DSR3)

      350
      • Figure 16-9. DMA Status Registers (DSRn)

        350
      • Table 16-4. DSRn Field Descriptions (continued)

        350
  • 16.5 DMA Controller Module Functional Description

    351
    • 16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)

      351
    • 16.5.2 Data Transfer Modes

      352
      • 16.5.2.1 Dual-Address Transfers

        352
    • 16.5.3 Channel Initialization and Startup

      353
      • 16.5.3.1 Channel Prioritization

        353
      • 16.5.3.2 Programming the DMA Controller Module

        353
    • 16.5.4 Data Transfer

      354
      • 16.5.4.1 Auto-Alignment

        354
      • 16.5.4.2 Bandwidth Control

        355
    • 16.5.5 Termination

      355
• Chapter 17 Fast Ethernet Controller (FEC)

  357
  • 17.1 Overview

    357
    • 17.1.1 Features

      357
  • 17.2 Modes of Operation

    358
    • 17.2.1 Full and Half Duplex Operation

      358
    • 17.2.2 Interface Options

      358
      • 17.2.2.1 10 Mbps and 100 Mbps MII Interface

        358
      • 17.2.2.2 10 Mpbs 7-Wire Interface Operation

        359
    • 17.2.3 Address Recognition Options

      359
    • 17.2.4 Internal Loopback

      359
  • 17.3 FEC Top-Level Functional Diagram

    360
    • Figure 17-1. FEC Block Diagram

      360
  • 17.4 Functional Description

    361
    • 17.4.1 Initialization Sequence

      362
      • 17.4.1.1 Hardware Controlled Initialization

        362
        • Table 17-1. ECR[ETHER_EN] De-Assertion Effect on FEC

          362
    • 17.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])

      362
      • Table 17-2. User Initialization (Before ECR[ETHER_EN]) (continued)

        362
      • Table 17-3. FEC User Initialization (Before ECR[ETHER_EN])

        363
    • 17.4.3 Microcontroller Initialization

      363
      • Table 17-4. Microcontroller Initialization

        363
    • 17.4.4 User Initialization (After Asserting ECR[ETHER_EN])

      363
    • 17.4.5 Network Interface Options

      364
      • Table 17-5. MII Mode

        364
      • Table 17-6. 7-Wire Mode Configuration

        364
    • 17.4.6 FEC Frame Transmission

      365
    • 17.4.7 FEC Frame Reception

      366
    • 17.4.8 Ethernet Address Recognition

      367
      • Figure 17-2. Ethernet Address Recognition-Receive Block Decisions

        368
      • Figure 17-3. Ethernet Address Recognitionq-Microcode Decisions

        369
    • 17.4.9 Hash Algorithm

      369
      • Table 17-7. Destination Address to 6-Bit Hash (continued)

        370
    • 17.4.10 Full Duplex Flow Control

      372
      • Table 17-8. PAUSE Frame Field Specification

        372
    • 17.4.11 Inter-Packet Gap (IPG) Time

      373
    • 17.4.12 Collision Handling

      373
    • 17.4.13 Internal and External Loopback

      373
    • 17.4.14 Ethernet Error-Handling Procedure

      374
      • 17.4.14.1 Transmission Errors

        374
      • 17.4.14.2 Reception Errors

        375
  • 17.5 Programming Model

    376
    • 17.5.1 Top Level Module Memory Map

      376
      • Table 17-9. Module Memory Map

        376
    • 17.5.2 Detailed Memory Map (Control/Status Registers)

      376
      • Table 17-10. FEC Register Memory Map (continued)

        376
    • 17.5.3 MIB Block Counters Memory Map

      377
      • Table 17-11. MIB Counters Memory Map (continued)

        378
    • 17.5.4 Registers

      379
      • 17.5.4.1 Ethernet Interrupt Event Register (EIR)

        379
        • Figure 17-4. Ethernet Interrupt Event Register (EIR)

          380
        • Table 17-12. EIR Field Descriptions (continued)

          380
      • 17.5.4.2 Interrupt Mask Register (EIMR)

        382
        • Figure 17-5. Interrupt Mask Register (EIMR)

          382
        • Table 17-13. EIMR Field Descriptions

          382
      • 17.5.4.3 Receive Descriptor Active Register (RDAR)

        382
        • Figure 17-6. Receive Descriptor Active Register (RDAR)

          383
        • Table 17-14. RDAR Field Descriptions

          383
      • 17.5.4.4 Transmit Descriptor Active Register (TDAR)

        383
        • Figure 17-7. Transmit Descriptor Active Register (TDAR)

          384
        • Table 17-15. TDAR Field Descriptions

          384
      • 17.5.4.5 Ethernet Control Register (ECR)

        384
        • Figure 17-8. Ethernet Control Register (ECR)

          384
        • Table 17-16. ECR Field Descriptions

          385
      • 17.5.4.6 MII Management Frame Register (MMFR)

        385
        • Figure 17-9. MII Management Frame Register (MMFR)

          385
        • Table 17-17. MMFR Field Descriptions

          386
      • 17.5.4.7 MII Speed Control Register (MSCR)

        387
        • Figure 17-10. MII Speed Control Register (MSCR)

          387
        • Table 17-18. MSCR Field Descriptions

          387
        • Table 17-19. Programming Examples for MSCR

          388
      • 17.5.4.8 MIB Control Register (MIBC)

        388
        • Figure 17-11. MIB Control Register (MIBC)

          388
        • Table 17-20. MIBC Field Descriptions

          388
      • 17.5.4.9 Receive Control Register (RCR)

        389
        • Figure 17-12. Receive Control Register (RCR)

          389
        • Table 17-21. RCR Field Descriptions (continued)

          389
      • 17.5.4.10 Transmit Control Register (TCR)

        390
        • Figure 17-13. Transmit Control Register (TCR)

          390
        • Table 17-22. TCR Field Descriptions

          391
      • 17.5.4.11 Physical Address Low Register (PALR)

        391
        • Figure 17-14. Physical Address Low Register (PALR)

          392
        • Table 17-23. PALR Field Descriptions

          392
      • 17.5.4.12 Physical Address High Register (PAUR)

        392
        • Figure 17-15. Physical Address High Register (PAUR)

          392
        • Table 17-24. PAUR Field Descriptions

          393
      • 17.5.4.13 Opcode/Pause Duration Register (OPD)

        393
        • Figure 17-16. Opcode/Pause Duration Register (OPD)

          393
        • Table 17-25. OPD Field Descriptions

          393
      • 17.5.4.14 Descriptor Individual Upper Address Register (IAUR)

        393
        • Figure 17-17. Descriptor Individual Upper Address Register (IAUR)

          394
        • Table 17-26. IAUR Field Descriptions

          394
      • 17.5.4.15 Descriptor Individual Lower Address (IALR)

        394
        • Figure 17-18. Descriptor Individual Lower Address Register (IALR)

          394
        • Table 17-27. IALR Field Descriptions

          395
      • 17.5.4.16 Descriptor Group Upper Address (GAUR)

        395
        • Figure 17-19. Descriptor Group Upper Address Register (GAUR)

          395
        • Table 17-28. GAUR Field Descriptions

          395
      • 17.5.4.17 Descriptor Group Lower Address (GALR)

        395
        • Figure 17-20. Descriptor Group Lower Address Register (GALR)

          396
        • Table 17-29. GALR Field Descriptions

          396
      • 17.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)

        396
        • Figure 17-21. FIFO Transmit FIFO Watermark Register (TFWR)

          396
        • Table 17-30. TFWR Field Descriptions

          397
      • 17.5.4.19 FIFO Receive Bound Register (FRBR)

        397
        • Figure 17-22. FIFO Receive Bound Register (FRBR)

          397
        • Table 17-31. FRBR Field Descriptions

          397
      • 17.5.4.20 FIFO Receive Start Register (FRSR)

        398
        • Figure 17-23. FIFO Receive Start Register (FRSR)

          398
        • Table 17-32. FRSR Field Descriptions

          398
      • 17.5.4.21 Receive Descriptor Ring Start (ERDSR)

        398
        • Figure 17-24. Receive Descriptor Ring Start Register (ERDSR)

          399
        • Table 17-33. ERDSR Field Descriptions

          399
      • 17.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR)

        399
        • Figure 17-25. Transmit Buffer Descriptor Ring Start Register (ETDSR)

          399
        • Table 17-34. ETDSR Field Descriptions

          400
      • 17.5.4.23 Receive Buffer Size Register (EMRBR)

        400
        • Figure 17-26. Receive Buffer Size Register (EMRBR)

          400
        • Table 17-35. EMRBR Field Descriptions

          400
  • 17.6 Buffer Descriptors

    401
    • 17.6.1 Driver/DMA Operation with Buffer Descriptors

      401
      • 17.6.1.1 Driver/DMA Operation with Transmit BDs

        401
      • 17.6.1.2 Driver/DMA Operation with Receive BDs

        402
    • 17.6.2 Ethernet Receive Buffer Descriptor (RxBD)

      403
      • Figure 17-27. Receive Buffer Descriptor (RxBD)

        403
      • Table 17-36. Receive Buffer Descriptor Field Definitions (continued)

        404
    • 17.6.3 Ethernet Transmit Buffer Descriptor (TxBD)

      405
      • Figure 17-28. Transmit Buffer Descriptor (TxBD)

        406
      • Table 17-37. Transmit Buffer Descriptor Field Definitions (continued)

        406
• Chapter 18 Watchdog Timer Module

  409
  • 18.1 Introduction

    409
  • 18.2 Low-Power Mode Operation

    409
    • Table 18-1. Watchdog Module Operation in Low-power Modes

      409
  • 18.3 Block Diagram

    410
    • Figure 18-1. Watchdog Timer Block Diagram

      410
  • 18.4 Signals

    410
  • 18.5 Memory Map and Registers

    410
    • 18.5.1 Memory Map

      410
      • Table 18-2. Watchdog Timer Module Memory Map

        411
    • 18.5.2 Registers

      411
      • 18.5.2.1 Watchdog Control Register (WCR)

        411
        • Figure 18-2. Watchdog Control Register (WCR)

          411
        • Table 18-3. WCR Field Descriptions

          412
      • 18.5.2.2 Watchdog Modulus Register (WMR)

        412
        • Figure 18-3. Watchdog Modulus Register (WMR)

          412
        • Table 18-4. WMR Field Descriptions

          413
      • 18.5.2.3 Watchdog Count Register (WCNTR)

        413
        • Figure 18-4. Watchdog Count Register (WCNTR)

          413
        • Table 18-5. WCNTR Field Descriptions

          413
      • 18.5.2.4 Watchdog Service Register (WSR)

        413
        • Figure 18-5. Watchdog Service Register (WSR)

          414
• Chapter 19 Programmable Interrupt Timer Modules (PIT0-PIT3)

  415
  • 19.1 Overview

    415
  • 19.2 Block Diagram

    415
    • Figure 19-1. PIT Block Diagram

      415
  • 19.3 Low-Power Mode Operation

    416
    • Table 19-1. PIT Module Operation in Low-power Modes

      416
  • 19.4 Signals

    416
  • 19.5 Memory Map and Registers

    417
    • 19.5.1 Memory Map

      417
      • Table 19-2. Programmable Interrupt Timer Modules Memory Map

        417
    • 19.5.2 Registers

      417
      • 19.5.2.1 PIT Control and Status Register (PCSR)

        418
        • Figure 19-2. PIT Control and Status Register (PCSR)

          418
        • Table 19-3. PCSR Field Descriptions (continued)

          418
      • 19.5.2.2 PIT Modulus Register (PMR)

        419
        • Figure 19-3. PIT Modulus Register (PMR)

          420
      • 19.5.2.3 PIT Count Register (PCNTR)

        420
        • Figure 19-4. PIT Count Register (PCNTR)

          420
  • 19.6 Functional Description

    420
    • 19.6.1 Set-and-Forget Timer Operation

      420
      • Figure 19-5. Counter Reloading from the Modulus Latch

        421
    • 19.6.2 Free-Running Timer Operation

      421
      • Figure 19-6. Counter in Free-Running Mode

        421
    • 19.6.3 Timeout Specifications

      421
  • 19.7 Interrupt Operation

    422
    • Table 19-4. PIT Interrupt Requests

      422
• Chapter 20 General Purpose Timer Modules (GPTA and GPTB)

  423
  • 20.1 Features

    423
  • 20.2 Block Diagram

    424
    • Figure 20-1. GPT Block Diagram

      424
  • 20.3 Low-Power Mode Operation

    425
    • Table 20-1. Watchdog Module Operation in Low-power Modes

      425
  • 20.4 Signal Description

    425
    • Table 20-2. Signal Properties

      425
    • 20.4.1 GPTn[2:0]

      425
    • 20.4.2 GPTn3

      426
    • 20.4.3 SYNCn

      426
  • 20.5 Memory Map and Registers

    426
    • Table 20-3. GPT Modules Memory Map (continued)

      426
    • 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)

      427
      • Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)

        427
      • Table 20-4. GPTIOS Field Descriptions

        428
    • 20.5.2 GPT Compare Force Register (GPCFORC)

      428
      • Figure 20-3. GPT Input Compare Force Register (GPCFORC)

        428
      • Table 20-5. GPTCFORC Field Descriptions

        428
    • 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)

      428
      • Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M)

        428
      • Table 20-6. GPTOC3M Field Descriptions

        429
    • 20.5.4 GPT Output Compare 3 Data Register (GPTOC3D)

      429
      • Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D)

        429
      • Table 20-7. GPTOC3D Field Descriptions

        429
    • 20.5.5 GPT Counter Register (GPTCNT)

      429
      • Figure 20-6. GPT Counter Register (GPTCNT)

        429
      • Table 20-8. GPTCNT Field Descriptions

        430
    • 20.5.6 GPT System Control Register 1 (GPTSCR1)

      430
      • Figure 20-7. GPT System Control Register 1 (GPTSCR1)

        430
      • Table 20-9. GPTSCR1 Field Descriptions

        430
      • Figure 20-8. Fast Clear Flag Logic

        431
    • 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)

      431
      • Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV)

        431
      • Table 20-10. GPTTOV Field Description

        431
    • 20.5.8 GPT Control Register 1 (GPTCTL1)

      431
      • Figure 20-10. GPT Control Register 1 (GPTCTL1)

        431
      • Table 20-11. GPTCL1 Field Descriptions

        432
    • 20.5.9 GPT Control Register 2 (GPTCTL2)

      432
      • Figure 20-11. GPT Control Register 2 (GPTCTL2)

        432
      • Table 20-12. GPTLCTL2 Field Descriptions

        432
    • 20.5.10 GPT Interrupt Enable Register (GPTIE)

      432
      • Figure 20-12. GPT Interrupt Enable Register (GPTIE)

        432
      • Table 20-13. GPTIE Field Descriptions

        433
    • 20.5.11 GPT System Control Register 2 (GPTSCR2)

      433
      • Figure 20-13. GPT System Control Register 2 (GPTSCR2)

        433
      • Table 20-14. GPTSCR2 Field Descriptions

        433
    • 20.5.12 GPT Flag Register 1 (GPTFLG1)

      434
      • Figure 20-14. GPT Flag Register 1 (GPTFLG1)

        434
      • Table 20-15. GPTFLG1 Field Descriptions

        434
    • 20.5.13 GPT Flag Register 2 (GPTFLG2)

      434
      • Figure 20-15. GPT Flag Register 2 (GPTFLG2)

        434
      • Table 20-16. GPTFLG2 Field Descriptions

        434
    • 20.5.14 GPT Channel Registers (GPTCn)

      435
      • Figure 20-16. GPT Channel[0:3] Register (GPTCn)

        435
      • Table 20-17. GPTCn Field Descriptions

        435
    • 20.5.15 Pulse Accumulator Control Register (GPTPACTL)

      435
      • Figure 20-17. Pulse Accumulator Control Register (GPTPACTL)

        435
      • Table 20-18. GPTPACTL Field Descriptions (continued)

        435
    • 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)

      436
      • Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG)

        436
      • Table 20-19. GPTPAFLG Field Descriptions

        437
    • 20.5.17 Pulse Accumulator Counter Register (GPTPACNT)

      437
      • Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)

        437
      • Table 20-20. GPTPACR Field Descriptions

        437
    • 20.5.18 GPT Port Data Register (GPTPORT)

      438
      • Figure 20-20. GPT Port Data Register (GPTPORT)

        438
      • Table 20-21. GPTPORT Field Descriptions

        438
    • 20.5.19 GPT Port Data Direction Register (GPTDDR)

      438
      • Figure 20-21. GPT Port Data Direction Register (GPTDDR)

        438
      • Table 20-22. GPTDDR Field Descriptions

        438
  • 20.6 Functional Description

    439
    • 20.6.1 Prescaler

      439
    • 20.6.2 Input Capture

      439
    • 20.6.3 Output Compare

      439
    • 20.6.4 Pulse Accumulator

      440
    • 20.6.5 Event Counter Mode

      440
    • 20.6.6 Gated Time Accumulation Mode

      441
      • Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic

        441
    • 20.6.7 General-Purpose I/O Ports

      441
      • Table 20-23. GPT Settings and Pin Functions (continued)

        442
  • 20.7 Reset

    443
  • 20.8 Interrupts

    443
    • Table 20-24. GPT Interrupt Requests

      443
    • 20.8.1 GPT Channel Interrupts (CnF)

      444
    • 20.8.2 Pulse Accumulator Overflow (PAOVF)

      444
    • 20.8.3 Pulse Accumulator Input (PAIF)

      444
    • 20.8.4 Timer Overflow (TOF)

      444
• Chapter 21 DMA Timers (DTIM0-DTIM3)

  447
  • 21.1 Overview

    447
    • Figure 21-1. DMA Timer Block Diagram

      448
    • 21.1.1 Key Features

      448
  • 21.2 DMA Timer Programming Model

    448
    • 21.2.1 Prescaler

      448
    • 21.2.2 Capture Mode

      449
    • 21.2.3 Reference Compare

      449
    • 21.2.4 Output Mode

      449
    • 21.2.5 Memory Map

      449
      • Table 21-1. DMA Timer Module Memory Map (continued)

        449
    • 21.2.6 DMA Timer Mode Registers (DTMRn)

      450
      • Figure 21-2. DTMRn Bit Definitions

        450
      • Table 21-2. DTMRn Field Descriptions

        451
    • 21.2.7 DMA Timer Extended Mode Registers (DTXMRn)

      451
      • Figure 21-3. DTXMRn Bit Definitions

        451
      • Table 21-3. DTXMRn Field Descriptions

        452
    • 21.2.8 DMA Timer Event Registers (DTERn)

      452
      • Figure 21-4. DTERn Bit Definitions

        452
      • Table 21-4. DTERn Field Descriptions

        453
    • 21.2.9 DMA Timer Reference Registers (DTRRn)

      453
      • Figure 21-5. DTRRn Bit Definitions

        453
    • 21.2.10 DMA Timer Capture Registers (DTCRn)

      453
      • Figure 21-6. DTCRn Bit Definitions

        454
    • 21.2.11 DMA Timer Counters (DTCNn)

      454
      • Figure 21-7. DTCNn Bit Definitions

        454
  • 21.3 Using the DMA Timer Modules

    454
    • 21.3.1 Code Example

      455
    • 21.3.2 Calculating Time-Out Values

      456
• Chapter 22 Queued Serial Peripheral Interface (QSPI) Module

  457
  • 22.1 Overview

    457
  • 22.2 Features

    457
  • 22.3 Module Description

    457
    • 22.3.1 Interface and Signals

      458
      • Figure 22-1. QSPI Block Diagram

        458
      • Table 22-1. QSPI Input and Output Signals and Functions

        459
    • 22.3.2 Internal Bus Interface

      459
  • 22.4 Operation

    459
    • 22.4.1 QSPI RAM

      460
      • Figure 22-2. QSPI RAM Model

        461
      • 22.4.1.1 Receive RAM

        461
      • 22.4.1.2 Transmit RAM

        462
      • 22.4.1.3 Command RAM

        462
    • 22.4.2 Baud Rate Selection

      462
      • Table 22-2. QSPI_CLK Frequency as Function of System Clock and Baud Rate

        463
    • 22.4.3 Transfer Delays

      463
    • 22.4.4 Transfer Length

      464
    • 22.4.5 Data Transfer

      464
  • 22.5 Programming Model

    465
    • Table 22-3. QSPI Registers

      465
    • 22.5.1 QSPI Mode Register (QMR)

      466
      • Figure 22-3. QSPI Mode Register (QMR)

        466
      • Table 22-4. QMR Field Descriptions (continued)

        466
      • Figure 22-4. QSPI Clocking and Data Transfer Example

        467
    • 22.5.2 QSPI Delay Register (QDLYR)

      467
      • Figure 22-5. QSPI Delay Register (QDLYR)

        467
      • Table 22-5. QDLYR Field Descriptions

        468
    • 22.5.3 QSPI Wrap Register (QWR)

      468
      • Figure 22-6. QSPI Wrap Register (QWR)

        468
      • Table 22-6. QWR Field Descriptions

        468
    • 22.5.4 QSPI Interrupt Register (QIR)

      469
      • Figure 22-7. QSPI Interrupt Register (QIR)

        469
      • Table 22-7. QIR Field Descriptions

        469
    • 22.5.5 QSPI Address Register (QAR)

      470
      • Figure 22-8. QSPI Address Register

        470
    • 22.5.6 QSPI Data Register (QDR)

      470
      • Figure 22-9. QSPI Data Register (QDR)

        470
    • 22.5.7 Command RAM Registers (QCR0-QCR15)

      471
      • Figure 22-10. Command RAM Registers (QCR0-QCR15)

        471
      • Table 22-8. QCR0-QCR15 Field Descriptions

        471
      • Figure 22-11. QSPI Timing

        472
    • 22.5.8 Programming Example

      472
• Chapter 23 UART Modules

  475
  • 23.1 Overview

    475
    • Figure 23-1. Simplified Block Diagram

      475
  • 23.2 Serial Module Overview

    476
  • 23.3 Register Descriptions

    477
    • Table 23-1. UART Module Memory Map (continued)

      477
    • 23.3.1 UART Mode Registers 1 (UMR1n)

      478
      • Figure 23-2. UART Mode Registers 1 (UMR1n)

        478
      • Table 23-2. UMR1n Field Descriptions

        479
    • 23.3.2 UART Mode Register 2 (UMR2n)

      480
      • Figure 23-3. UART Mode Register 2 (UMR2n)

        480
      • Table 23-3. UMR2n Field Descriptions (continued)

        480
    • 23.3.3 UART Status Registers (USRn)

      481
      • Figure 23-4. UART Status Register (USRn)

        481
      • Table 23-4. USRn Field Descriptions (continued)

        481
    • 23.3.4 UART Clock Select Registers (UCSRn)

      482
      • Figure 23-5. UART Clock Select Register (UCSRn)

        482
      • Table 23-5. UCSRn Field Descriptions

        483
    • 23.3.5 UART Command Registers (UCRn)

      483
      • Figure 23-6. UART Command Register (UCRn)

        483
      • Table 23-6. UCRn Field Descriptions (continued)

        484
    • 23.3.6 UART Receive Buffers (URBn)

      485
      • Figure 23-7. UART Receive Buffer (URBn)

        485
    • 23.3.7 UART Transmit Buffers (UTBn)

      485
      • Figure 23-8. UART Transmit Buffer (UTBn)

        486
    • 23.3.8 UART Input Port Change Registers (UIPCRn)

      486
      • Figure 23-9. UART Input Port Change Register (UIPCRn)

        486
      • Table 23-7. UIPCRn Field Descriptions

        486
    • 23.3.9 UART Auxiliary Control Register (UACRn)

      487
      • Figure 23-10. UART Auxiliary Control Register (UACRn)

        487
      • Table 23-8. UACRn Field Descriptions

        487
    • 23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)

      487
      • Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)

        487
      • Table 23-9. UISRn/UIMRn Field Descriptions

        488
    • 23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)

      488
      • Figure 23-12. UART Baud Rate Generator Register (UBG1n)

        488
      • Figure 23-13. UART Baud Rate Generator Register (UBG2n)

        488
    • 23.3.12 UART Input Port Register (UIPn)

      489
      • Figure 23-14. UART Input Port Register (UIPn)

        489
      • Table 23-10. UIPn Field Descriptions

        489
    • 23.3.13 UART Output Port Command Registers (UOP1n/UOP0n)

      489
      • Figure 23-15. UART Output Port Command Registers (UOP1n/UOP0n)

        489
      • Table 23-11. UOP1/UOP0 Field Descriptions

        490
  • 23.4 UART Module Signal Definitions

    491
    • Figure 23-16. UART Block Diagram Showing External and Internal Interface Signals

      491
    • Table 23-12. UART Module Signals

      492
    • Figure 23-17. UART/RS-232 Interface

      492
  • 23.5 Operation

    492
    • 23.5.1 Transmitter/Receiver Clock Source

      492
      • 23.5.1.1 Programmable Divider

        492
        • Figure 23-18. Clocking Source Diagram

          493
      • 23.5.1.2 Calculating Baud Rates

        493
    • 23.5.2 Transmitter and Receiver Operating Modes

      494
      • Figure 23-19. Transmitter and Receiver Functional Diagram

        494
      • 23.5.2.1 Transmitter

        494
        • Figure 23-20. Transmitter Timing Diagram

          496
      • 23.5.2.2 Receiver

        496
        • Figure 23-21. Receiver Timing

          497
      • 23.5.2.3 FIFO Stack

        497
    • 23.5.3 Looping Modes

      499
      • 23.5.3.1 Automatic Echo Mode

        499
        • Figure 23-22. Automatic Echo

          499
      • 23.5.3.2 Local Loop-Back Mode

        499
        • Figure 23-23. Local Loop-Back

          499
      • 23.5.3.3 Remote Loop-Back Mode

        500
        • Figure 23-24. Remote Loop-Back

          500
    • 23.5.4 Multidrop Mode

      500
      • Figure 23-25. Multidrop Mode Timing Diagram

        501
    • 23.5.5 Bus Operation

      502
      • 23.5.5.1 Read Cycles

        502
      • 23.5.5.2 Write Cycles

        502
    • 23.5.6 Programming

      502
      • 23.5.6.1 Interrupt and DMA Request Initialization

        503
        • Table 23-13. UART Interrupts

          503
        • Table 23-14. UART DMA Requests

          504
      • 23.5.6.2 UART Module Initialization Sequence

        504
        • Table 23-15. UART Module Initialization Sequence

          504
        • Figure 23-26. UART Mode Programming Flowchart (Sheet 5 of 5)

          505
• Chapter 24 I2C Interface

  511
  • 24.1 Overview

    511
  • 24.2 Interface Features

    511
    • Figure 24-1. I2C Module Block Diagram

      512
  • 24.3 I2C System Configuration

    513
  • 24.4 I2C Protocol

    513
    • Figure 24-2. I2C Standard Communication Protocol

      513
    • Figure 24-3. Repeated START

      514
    • 24.4.1 Arbitration Procedure

      514
    • 24.4.2 Clock Synchronization

      515
      • Figure 24-4. Synchronized Clock SCL

        515
    • 24.4.3 Handshaking

      515
    • 24.4.4 Clock Stretching

      515
  • 24.5 Programming Model

    516
    • Table 24-1. I2C Interface Memory Map

      516
    • 24.5.1 I2C Address Register (I2ADR)

      516
      • Figure 24-5. I2C Address Register (I2ADR)

        516
      • Table 24-2. I2ADR Field Descriptions

        516
    • 24.5.2 I2C Frequency Divider Register (I2FDR)

      517
      • Figure 24-6. I2C Frequency Divider Register (I2FDR)

        517
      • Table 24-3. I2FDR Field Descriptions

        517
    • 24.5.3 I2C Control Register (I2CR)

      518
      • Figure 24-7. I2C Control Register (I2CR)

        518
      • Table 24-4. I2CR Field Descriptions

        518
    • 24.5.4 I2C Status Register (I2SR)

      519
      • Figure 24-8. I2CR Status Register (I2SR)

        519
      • Table 24-5. I2SR Field Descriptions (continued)

        519
    • 24.5.5 I2C Data I/O Register (I2DR)

      520
      • Figure 24-9. I2C Data I/O Register (I2DR)

        520
  • 24.6 I2C Programming Examples

    520
    • 24.6.1 Initialization Sequence

      520
    • 24.6.2 Generation of START

      521
    • 24.6.3 Post-Transfer Software Response

      521
    • 24.6.4 Generation of STOP

      522
    • 24.6.5 Generation of Repeated START

      523
    • 24.6.6 Slave Mode

      523
    • 24.6.7 Arbitration Lost

      524
      • Figure 24-10. Flow-Chart of Typical I2C Interrupt Routine

        525
• Chapter 25 FlexCAN

  527
  • 25.1 Features

    527
    • Figure 25-1. FlexCAN Block Diagram and Pinout

      528
    • 25.1.1 FlexCAN Memory Map

      529
      • Table 25-1. FlexCAN Memory Map

        529
    • 25.1.2 External Signals

      529
  • 25.2 The CAN System

    530
    • Figure 25-2. Typical CAN system

      530
  • 25.3 Message Buffers

    530
    • 25.3.1 Message Buffer Structure

      530
      • Figure 25-3. Extended ID Message Buffer Structure

        531
      • Figure 25-4. Standard ID Message Buffer Structure

        531
      • 25.3.1.1 Common Fields for Extended and Standard Format Frames

        531
        • Table 25-2. Common Extended/Standard Format Frames

          532
        • Table 25-3. Message Buffer Codes for Receive Buffers

          532
        • Table 25-4. Message Buffer Codes for Transmit Buffers

          532
      • 25.3.1.2 Fields for Extended Format Frames

        533
        • Table 25-5. Extended Format Frames

          533
      • 25.3.1.3 Fields for Standard Format Frames

        533
        • Table 25-6. Standard Format Frames

          533
    • 25.3.2 Message Buffer Memory Map

      533
      • Figure 25-5. FlexCAN Memory Map

        534
  • 25.4 Functional Overview

    534
    • 25.4.1 Transmit Process

      535
    • 25.4.2 Receive Process

      535
      • 25.4.2.1 Self-Received Frames

        536
    • 25.4.3 Message Buffer Handling

      536
      • 25.4.3.1 Serial Message Buffers (SMBs)

        537
      • 25.4.3.2 Transmit Message Buffer Deactivation

        537
      • 25.4.3.3 Receive Message Buffer Deactivation

        537
      • 25.4.3.4 Locking and Releasing Message Buffers

        538
    • 25.4.4 Remote Frames

      538
    • 25.4.5 Overload Frames

      539
    • 25.4.6 Time Stamp

      539
    • 25.4.7 Listen-Only Mode

      539
    • 25.4.8 Bit Timing

      540
      • Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock

        540
      • 25.4.8.1 Configuring the FlexCAN Bit Timing

        540
    • 25.4.9 FlexCAN Error Counters

      541
    • 25.4.10 FlexCAN Initialization Sequence

      542
    • 25.4.11 Special Operating Modes

      543
      • 25.4.11.1 Debug Mode

        543
      • 25.4.11.2 Low-Power Stop Mode for Power Saving

        543
      • 25.4.11.3 Auto-Power Save Mode

        545
    • 25.4.12 Interrupts

      545
  • 25.5 Programmer’s Model

    546
    • 25.5.1 CAN Module Configuration Register (CANMCR)

      546
      • Figure 25-6. CAN Module Configuration Register (CANMCR)

        546
      • Table 25-8. CANMCR Field Descriptions (continued)

        547
    • 25.5.2 FlexCAN Control Register 0 (CANCTRL0)

      548
      • Figure 25-7. FlexCAN Control Register 0 (CANCTRL0)

        548
      • Table 25-9. CANCTRL0 Field Descriptions

        549
      • Table 25-10. Transmit Pin Configuration

        549
    • 25.5.3 FlexCAN Control Register 1 (CANCTRL1)

      549
      • Figure 25-8. FlexCAN Control Register 1 (CANCTRL1)

        549
      • Table 25-11. CANCTRL1 Field Descriptions

        550
    • 25.5.4 Prescaler Divide Register (PRESDIV)

      550
      • Figure 25-9. Prescaler Divide Register (PRESDIV)

        550
      • Table 25-12. PRESDIV Field Descriptions

        551
    • 25.5.5 FlexCAN Control Register 2 (CANCTRL2)

      551
      • Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)

        551
      • Table 25-13. CANCTRL2 Field Descriptions

        551
    • 25.5.6 Free Running Timer (TIMER)

      552
      • Figure 25-11. Free Running Timer (TIMER)

        552
      • Table 25-14. TIMER Field Descriptions

        552
    • 25.5.7 Rx Mask Registers

      552
      • Table 25-15. Mask examples for Normal/Extended Messages (continued)

        552
      • 25.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK)

        553
        • Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)

          553
        • Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions

          554
    • 25.5.8 FlexCAN Error and Status Register (ESTAT)

      554
      • Figure 25-13. FlexCAN Error and Status Register (ESTAT)

        554
      • Table 25-17. ESTAT Field Descriptions (continued)

        555
    • 25.5.9 Interrupt Mask Register (IMASK)

      556
      • Figure 25-14. Interrupt Mask Register (IMASK)

        556
      • Table 25-18. IMASK Field Descriptions

        557
    • 25.5.10 Interrupt Flag Register (IFLAG)

      557
      • Figure 25-15. Interrupt Flag Register (IFLAG)

        557
      • Table 25-19. IFLAG Field Descriptions

        557
    • 25.5.11 FlexCAN Receive Error Counter (RXECTR)

      558
      • Figure 25-16. FlexCAN Receive Error Counter (RXECTR)

        558
      • Table 25-20. RXECTR Field Descriptions

        558
    • 25.5.12 FlexCAN Transmit Error Counter (TXECTR)

      558
      • Figure 25-17. FlexCAN Transmit Error Counter (TXECTR)

        558
      • Table 25-21. TXECTR Field Descriptions

        558
• Chapter 26 General Purpose I/O Module

  559
  • 26.1 Introduction

    559
    • Figure 26-1. MCF5282 Ports Module Block Diagram

      560
    • 26.1.1 Overview

      561
    • 26.1.2 Features

      561
    • 26.1.3 Modes of Operation

      561
  • 26.2 External Signal Description

    562
    • Table 26-1. MCF5282 Ports External Signals (continued)

      562
  • 26.3 Memory Map/Register Definition

    564
    • 26.3.1 Register Overview

      564
      • Table 26-2. MCF5282 Ports Module Memory Map (continued)

        564
    • 26.3.2 Register Descriptions

      566
      • 26.3.2.1 Port Output Data Registers (PORTn)

        566
        • Figure 26-2. Port Output Data Registers (8-bit)

          566
        • Figure 26-3. Port Output Data Register (7-bit)

          566
        • Figure 26-4. Port Output Data Registers (6-bit)

          566
        • Figure 26-5. Port Output Data Registers (4-bit)

          567
        • Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions

          567
      • 26.3.2.2 Port Data Direction Registers (DDRn)

        567
        • Figure 26-6. Port Data Direction Registers (8-bit)

          567
        • Figure 26-7. Port Data Direction Register (7-bit)

          568
        • Figure 26-8. Port Data Direction Registers (6-bit)

          568
        • Figure 26-9. Port Data Direction Registers (4-bit)

          568
        • Table 26-4. DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions

          568
      • 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)

        569
        • Figure 26-10. Port Pin Data/Set Data Registers (8-bit)

          569
        • Figure 26-11. Port Pin Data/Set Data Register (7-bit)

          569
        • Figure 26-12. Port Pin Data/Set Data Registers (6-bit)

          569
        • Figure 26-13. Port Pin Data/Set Data Registers (4-bit)

          570
        • Table 26-5. PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions

          570
      • 26.3.2.4 Port Clear Output Data Registers (CLRn)

        570
        • Figure 26-14. Port Clear Output Data Registers (8-bit)

          570
        • Figure 26-15. Port Clear Output Data Register (7-bit)

          571
        • Figure 26-16. Port Clear Output Data Registers (6-bit)

          571
        • Figure 26-17. Port Clear Output Data Registers (4-bit)

          571
        • Table 26-6. CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions

          571
      • 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)

        572
        • Figure 26-18. Port B/C/D Pin Assignment Register (PBCDPAR)

          572
        • Table 26-7. PBCDPAR Field Descriptions

          572
        • Table 26-8. Reset Values for PBCDPAR Bits

          572
      • 26.3.2.6 Port E Pin Assignment Register (PEPAR)

        573
        • Figure 26-19. Port E Pin Assignment Register (PEPAR)

          573
        • Table 26-9. PEPAR Field Descriptions (continued)

          573
        • Table 26-10. Reset Values for PEPAR Bits and Fields

          574
      • 26.3.2.7 Port F Pin Assignment Register (PFPAR)

        575
        • Figure 26-20. Port F Pin Assignment Register (PFPAR)

          575
        • Table 26-11. PFPAR Field Descriptions

          575
      • 26.3.2.8 Port J Pin Assignment Register (PJPAR)

        576
        • Figure 26-21. Port J Pin Assignment Register (PJPAR)

          576
        • Table 26-12. PJPAR Field Descriptions

          576
      • 26.3.2.9 Port SD Pin Assignment Register (PSDPAR)

        577
        • Figure 26-22. Port SD Pin Assignment Register (PSDPAR)

          577
        • Table 26-13. PSDPAR Field Descriptions

          577
      • 26.3.2.10 Port AS Pin Assignment Register (PASPAR)

        577
        • Figure 26-23. Port AS Pin Assignment Register (PASPAR)

          577
        • Table 26-14. PASPAR Field Descriptions

          578
      • 26.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR)

        578
        • Figure 26-24. Port EH/EL Pin Assignment Register (PEHLPAR)

          578
        • Table 26-15. PEHLPAR Field Descriptions

          579
      • 26.3.2.12 Port QS Pin Assignment Register (PQSPAR)

        579
        • Figure 26-25. Port QS Pin Assignment Register (PQSPAR)

          579
        • Table 26-16. PQSPAR Field Description (continued)

          579
      • 26.3.2.13 Port TC Pin Assignment Register (PTCPAR)

        580
        • Figure 26-26. Port TC Pin Assignment Register (PTCPAR)

          580
        • Table 26-17. PTCPAR Field Descriptions (continued)

          580
      • 26.3.2.14 Port TD Pin Assignment Register (PTDPAR)

        581
        • Figure 26-27. Port TD Pin Assignment Register (PTDPAR)

          581
        • Table 26-18. PTDPAR Field Descriptions (continued)

          581
      • 26.3.2.15 Port UA Pin Assignment Register (PUAPAR)

        582
        • Figure 26-28. Port UA Pin Assignment Register (PUAPAR)

          582
        • Table 26-19. PUAPAR Field Descriptions

          582
  • 26.4 Functional Description

    583
    • 26.4.1 Overview

      583
    • 26.4.2 Port Digital I/O Timing

      583
      • Figure 26-29. Digital Input Timing

        583
      • Figure 26-30. Digital Output Timing

        584
  • 26.5 Initialization/Application Information

    584
• Chapter 27 Queued Analog-to-Digital Converter (QADC)

  585
  • 27.1 Features

    585
  • 27.2 Block Diagram

    586
    • Figure 27-1. QADC Block Diagram

      586
  • 27.3 Modes of Operation

    587
    • 27.3.1 Debug Mode

      587
    • 27.3.2 Stop Mode

      587
  • 27.4 Signals

    588
    • 27.4.1 Port QA Signal Functions

      588
      • 27.4.1.1 Port QA Analog Input Signals

        588
        • Figure 27-2. QADC Input and Output Signals

          589
      • 27.4.1.2 Port QA Digital Input/Output Signals

        589
    • 27.4.2 Port QB Signal Functions

      589
      • 27.4.2.1 Port QB Analog Input Signals

        589
      • 27.4.2.2 Port QB Digital I/O Signals

        590
    • 27.4.3 External Trigger Input Signals

      590
    • 27.4.4 Multiplexed Address Output Signals

      590
    • 27.4.5 Multiplexed Analog Input Signals

      590
      • Table 27-1. Multiplexed Analog Input Channels

        591
    • 27.4.6 Voltage Reference Signals

      591
    • 27.4.7 Dedicated Analog Supply Signals

      591
    • 27.4.8 Dedicated Digital I/O Port Supply Signal

      591
  • 27.5 Memory Map

    591
    • Table 27-2. QADC Memory Map

      592
  • 27.6 Register Descriptions

    592
    • 27.6.1 QADC Module Configuration Register (QADCMCR)

      592
      • Figure 27-3. QADC Module Configuration Register (QADCMCR)

        593
      • Table 27-3. QADCMCR Field Descriptions

        593
    • 27.6.2 QADC Test Register (QADCTEST)

      593
    • 27.6.3 Port Data Registers (PORTQA and PORTQB)

      593
      • Figure 27-4. QADC Port QA Data Register (PORTQA)

        594
      • Figure 27-5. QADC Port QB Data Register (PORTQB)

        594
    • 27.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)

      594
      • Figure 27-6. QADC Port QA Data Direction Register (DDRQA)

        595
      • Figure 27-7. Port QB Data Direction Register (DDRQB)

        595
    • 27.6.5 Control Registers

      595
      • 27.6.5.1 QADC Control Register 0 (QACR0)

        595
        • Figure 27-8. QADC Control Register 0 (QACR0)

          596
        • Table 27-4. QACR0 Field Descriptions

          596
        • Table 27-5. Prescaler fSYS Divide-by Values

          597
      • 27.6.5.2 QADC Control Register 1 (QACR1)

        598
        • Figure 27-9. QADC Control Register 1 (QACR1)

          598
        • Table 27-6. QACR1 Field Descriptions

          598
        • Table 27-7. Queue 1 Operating Modes

          599
      • 27.6.5.3 QADC Control Register 2 (QACR2)

        600
        • Figure 27-10. QADC Control Register 2 (QACR2)

          601
        • Table 27-8. QACR2 Field Descriptions

          602
        • Table 27-9. Queue 2 Operating Modes (continued)

          602
    • 27.6.6 Status Registers

      603
      • 27.6.6.1 QADC Status Register 0 (QASR0)

        603
        • Figure 27-11. QADC Status Register 0 (QASR0)

          606
        • Table 27-10. QASR0 Field Descriptions

          607
        • Table 27-11. CCW Pause Bit Response

          607
        • Table 27-12. Queue Status

          608
        • Figure 27-12. Queue Status Transition

          609
      • 27.6.6.2 QADC Status Register 1 (QASR1)

        610
        • Figure 27-13. QADC Status Register 1 (QASR1)

          610
        • Table 27-13. QASR1 Field Descriptions

          610
    • 27.6.7 Conversion Command Word Table (CCW)

      610
      • Figure 27-14. Conversion Command Word Table (CCW)

        611
      • Table 27-14. CCW Field Descriptions (continued)

        611
      • Table 27-15. Input Sample Times

        612
      • Table 27-16. Non-Multiplexed Channel Assignments and Signal Designations

        612
      • Table 27-17. Multiplexed Channel Assignments and Signal Designations

        613
    • 27.6.8 Result Registers

      613
      • 27.6.8.1 Right-Justified Unsigned Result Register (RJURR)

        613
        • Figure 27-15. Right-Justified Unsigned Result Register (RJURR)

          613
        • Table 27-18. RJURR Field Descriptions

          614
      • 27.6.8.2 Left-Justified Signed Result Register (LJSRR)

        614
        • Figure 27-16. Left-Justified Signed Result Register (LJSRR)

          614
        • Table 27-19. LJSRR Field Descriptions

          614
      • 27.6.8.3 Left-Justified Unsigned Result Register (LJURR)

        614
        • Figure 27-17. Left-Justified Unsigned Result Register (LJURR)

          615
        • Table 27-20. LJURR Field Descriptions

          615
  • 27.7 Functional Description

    615
    • 27.7.1 Result Coherency

      615
    • 27.7.2 External Multiplexing

      615
      • 27.7.2.1 External Multiplexing Operation

        616
        • Figure 27-18. External Multiplexing Configuration

          617
      • 27.7.2.2 Module Version Options

        618
        • Table 27-21. Analog Input Channels

          618
    • 27.7.3 Analog Subsystem

      618
      • 27.7.3.1 Analog-to-Digital Converter Operation

        618
        • Figure 27-19. QADC Analog Subsystem Block Diagram

          619
      • 27.7.3.2 Conversion Cycle Times

        619
        • Figure 27-20. Conversion Timing

          620
        • Figure 27-21. Bypass Mode Conversion Timing

          620
      • 27.7.3.3 Channel Decode and Multiplexer

        620
      • 27.7.3.4 Sample Buffer

        620
      • 27.7.3.5 Comparator

        621
      • 27.7.3.6 Bias

        621
      • 27.7.3.7 Successive Approximation Register (SAR)

        621
      • 27.7.3.8 State Machine

        621
  • 27.8 Digital Control Subsystem

    621
    • 27.8.1 Queue Priority Timing Examples

      622
      • 27.8.1.1 Queue Priority

        622
        • Figure 27-22. QADC Queue Operation with Pause

          623
      • 27.8.1.2 Queue Priority Schemes

        624
        • Table 27-22. Trigger Events

          624
        • Table 27-23. Status Bits

          624
        • Figure 27-23. CCW Priority Situation 1

          625
        • Figure 27-24. CCW Priority Situation 2

          626
        • Figure 27-25. CCW Priority Situation 3

          626
        • Figure 27-26. CCW Priority Situation 4

          627
        • Figure 27-27. CCW Priority Situation 5

          627
        • Figure 27-28. CCW Priority Situation 6

          628
        • Figure 27-29. CCW Priority Situation 7

          628
        • Figure 27-30. CCW Priority Situation 8

          629
        • Figure 27-31. CCW Priority Situation 9

          629
        • Figure 27-32. CCW Priority Situation 10

          630
        • Figure 27-33. CCW Priority Situation 11

          630
        • Figure 27-34. CCW Freeze Situation 12

          631
        • Figure 27-35. CCW Freeze Situation 13

          631
        • Figure 27-36. CCW Freeze Situation 14

          631
        • Figure 27-37. . CCW Freeze Situation 15

          631
        • Figure 27-38. CCW Freeze Situation 16

          632
        • Figure 27-39. CCW Freeze Situation 17

          632
        • Figure 27-40. CCW Freeze Situation 18

          632
        • Figure 27-41. CCW Freeze Situation 19

          632
    • 27.8.2 Boundary Conditions

      633
    • 27.8.3 Scan Modes

      634
    • 27.8.4 Disabled Mode

      634
    • 27.8.5 Reserved Mode

      634
    • 27.8.6 Single-Scan Modes

      634
      • 27.8.6.1 Software-Initiated Single-Scan Mode

        635
      • 27.8.6.2 Externally Triggered Single-Scan Mode

        636
      • 27.8.6.3 Externally Gated Single-Scan Mode

        636
      • 27.8.6.4 Interval Timer Single-Scan Mode

        637
    • 27.8.7 Continuous-Scan Modes

      638
      • 27.8.7.1 Software-Initiated Continuous-Scan Mode

        639
      • 27.8.7.2 Externally Triggered Continuous-Scan Mode

        640
      • 27.8.7.3 Externally Gated Continuous-Scan Mode

        640
      • 27.8.7.4 Periodic Timer Continuous-Scan Mode

        641
    • 27.8.8 QADC Clock (QCLK) Generation

      641
      • Figure 27-42. QADC Clock Subsystem Functions

        642
    • 27.8.9 Periodic/Interval Timer

      642
    • 27.8.10 Conversion Command Word Table

      643
      • Figure 27-43. QADC Conversion Queue Operation

        644
    • 27.8.11 Result Word Table

      646
  • 27.9 Signal Connection Considerations

    646
    • 27.9.1 Analog Reference Signals

      647
    • 27.9.2 Analog Power Signals

      647
      • Figure 27-44. Equivalent Analog Input Circuitry

        647
      • Figure 27-45. Errors Resulting from Clipping

        648
    • 27.9.3 Conversion Timing Schemes

      648
      • Figure 27-46. External Positive Edge Trigger Mode Timing with Pause

        649
      • Figure 27-47. Gated Mode, Single Scan Timing

        650
      • Figure 27-48. Gated Mode, Continuous Scan Timing

        651
    • 27.9.4 Analog Supply Filtering and Grounding

      651
      • Figure 27-49. Star-Ground at the Point of Power Supply Origin

        652
    • 27.9.5 Accommodating Positive/Negative Stress Conditions

      653
      • Figure 27-50. Input Signal Subjected to Negative Stress

        653
      • Figure 27-51. Input Signal Subjected to Positive Stress

        654
    • 27.9.6 Analog Input Considerations

      655
      • Figure 27-52. External Multiplexing of Analog Signal Sources

        656
    • 27.9.7 Analog Input Pins

      657
      • Figure 27-53. Electrical Model of an A/D Input Signal

        657
      • 27.9.7.1 Settling Time for the External Circuit

        658
        • Table 27-24. External Circuit Settling Time to 1/2 LSB

          658
      • 27.9.7.2 Error Resulting from Leakage

        659
        • Table 27-25. Error Resulting from Input Leakage (IOff)

          659
  • 27.10 Interrupts

    659
    • 27.10.1 Interrupt Operation

      659
      • Table 27-26. QADC Status Flags and Interrupt Sources

        660
    • 27.10.2 Interrupt Sources

      660
• Chapter 28 Reset Controller Module

  661
  • 28.1 Features

    661
  • 28.2 Block Diagram

    662
    • Figure 28-1. Reset Controller Block Diagram

      662
  • 28.3 Signals

    662
    • Table 28-1. Reset Controller Signal Properties

      662
    • 28.3.1 RSTI

      662
    • 28.3.2 RSTO

      662
  • 28.4 Memory Map and Registers

    663
    • Table 28-2. Reset Controller Memory Map

      663
    • 28.4.1 Reset Control Register (RCR)

      663
      • Figure 28-2. Reset Control Register (RCR)

        663
      • Table 28-3. RCR Field Descriptions (continued)

        663
    • 28.4.2 Reset Status Register (RSR)

      664
      • Figure 28-3. Reset Status Register (RSR)

        664
      • Table 28-4. RSR Field Descriptions

        665
  • 28.5 Functional Description

    666
    • 28.5.1 Reset Sources

      666
      • Table 28-5. Reset Source Summary

        666
      • 28.5.1.1 Power-On Reset

        666
      • 28.5.1.2 External Reset

        667
      • 28.5.1.3 Watchdog Timer Reset

        667
      • 28.5.1.4 Loss-of-Clock Reset

        667
      • 28.5.1.5 Loss-of-Lock Reset

        667
      • 28.5.1.6 Software Reset

        667
      • 28.5.1.7 LVD Reset

        667
    • 28.5.2 Reset Control Flow

      668
      • Figure 28-4. Reset Control Flow

        669
      • 28.5.2.1 Synchronous Reset Requests

        670
      • 28.5.2.2 Internal Reset Request

        670
      • 28.5.2.3 Power-On Reset/Low-Voltage Detect Reset

        670
    • 28.5.3 Concurrent Resets

      670
      • 28.5.3.1 Reset Flow

        670
      • 28.5.3.2 Reset Status Flags

        671
• Chapter 29 Debug Support

  673
  • 29.1 Overview

    673
    • Figure 29-1. Processor/Debug Module Interface

      673
  • 29.2 Signal Description

    674
    • Table 29-1. Debug Module Signals

      674
    • Figure 29-2. CLKOUT Timing

      674
  • 29.3 Real-Time Trace Support

    675
    • Table 29-2. Processor Status Encoding (continued)

      675
    • 29.3.1 Begin Execution of Taken Branch (PST = 0x5)

      676
      • Figure 29-3. Example JMP Instruction Output on PST/DDATA

        677
  • 29.4 Programming Model

    677
    • Figure 29-4. Debug Programming Model

      678
    • Table 29-3. BDM/Breakpoint Registers

      679
    • 29.4.1 Revision A Shared Debug Resources

      679
      • Table 29-4. Rev. A Shared BDM/Breakpoint Hardware

        679
    • 29.4.2 Address Attribute Trigger Register (AATR)

      680
      • Figure 29-5. Address Attribute Trigger Register (AATR)

        680
      • Table 29-5. AATR Field Descriptions (continued)

        680
    • 29.4.3 Address Breakpoint Registers (ABLR, ABHR)

      681
      • Figure 29-6. Address Breakpoint Registers (ABLR, ABHR)

        681
      • Table 29-6. ABLR Field Description

        682
      • Table 29-7. ABHR Field Description

        682
    • 29.4.4 Configuration/Status Register (CSR)

      682
      • Figure 29-7. Configuration/Status Register (CSR)

        682
      • Table 29-8. CSR Field Descriptions (continued)

        683
    • 29.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)

      684
      • Figure 29-8. Data Breakpoint/Mask Registers (DBR/DBMR)

        684
      • Table 29-9. DBR Field Descriptions

        685
      • Table 29-10. DBMR Field Descriptions

        685
      • Table 29-11. Access Size and Operand Data Location

        685
    • 29.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)

      685
      • Figure 29-9. Program Counter Breakpoint Register (PBR)

        686
      • Table 29-12. PBR Field Descriptions

        686
      • Figure 29-10. Program Counter Breakpoint Mask Register (PBMR)

        686
      • Table 29-13. PBMR Field Descriptions

        686
    • 29.4.7 Trigger Definition Register (TDR)

      686
      • Figure 29-11. Trigger Definition Register (TDR)

        687
      • Table 29-14. TDR Field Descriptions (continued)

        687
  • 29.5 Background Debug Mode (BDM)

    688
    • 29.5.1 CPU Halt

      688
    • 29.5.2 BDM Serial Interface

      690
      • Figure 29-12. BDM Serial Interface Timing

        690
      • 29.5.2.1 Receive Packet Format

        691
        • Figure 29-13. Receive BDM Packet

          691
        • Table 29-15. Receive BDM Packet Field Description

          691
      • 29.5.2.2 Transmit Packet Format

        691
        • Figure 29-14. Transmit BDM Packet

          691
        • Table 29-16. Transmit BDM Packet Field Description

          691
    • 29.5.3 BDM Command Set

      692
      • Table 29-17. BDM Command Summary

        692
      • 29.5.3.1 ColdFire BDM Command Format

        693
        • Figure 29-15. BDM Command Format

          693
        • Table 29-18. BDM Field Descriptions

          693
      • 29.5.3.2 Command Sequence Diagrams

        694
        • Figure 29-16. Command Sequence Diagram

          694
      • 29.5.3.3 Command Set Descriptions

        695
        • Figure 29-17. rareg/rdreg Command Format

          695
        • Figure 29-18. rareg/rdreg Command Sequence

          695
        • Figure 29-19. wareg/wdreg Command Format

          696
        • Figure 29-20. wareg/wdreg Command Sequence

          696
        • Figure 29-21. read Command/Result Formats

          697
        • Figure 29-22. read Command Sequence

          697
        • Figure 29-23. write Command Format

          698
        • Figure 29-24. write Command Sequence

          699
        • Figure 29-25. dump Command/Result Formats

          700
        • Figure 29-26. dump Command Sequence

          701
        • Figure 29-27. fill Command Format

          702
        • Figure 29-28. fill Command Sequence

          702
        • Figure 29-29. go Command Format

          703
        • Figure 29-30. go Command Sequence

          703
        • Figure 29-31. nop Command Format

          703
        • Figure 29-32. nop Command Sequence

          703
        • Figure 29-33. rcreg Command/Result Formats

          704
        • Table 29-19. Control Register Map

          704
        • Figure 29-34. rcreg Command Sequence

          705
        • Figure 29-35. wcreg Command/Result Formats

          706
        • Figure 29-36. wcreg Command Sequence

          707
        • Figure 29-37. rdmreg Command/Result Formats

          707
        • Table 29-20. Definition of DRc Encoding-Read

          708
        • Figure 29-38. rdmreg Command Sequence

          708
        • Figure 29-39. wdmreg BDM Command Format

          708
        • Figure 29-40. wdmreg Command Sequence

          708
  • 29.6 Real-Time Debug Support

    709
    • 29.6.1 Theory of Operation

      709
      • Table 29-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response

        709
      • 29.6.1.1 Emulator Mode

        710
    • 29.6.2 Concurrent BDM and Processor Operation

      711
  • 29.7 Processor Status, DDATA Definition

    712
    • 29.7.1 User Instruction Set

      712
      • Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued)

        712
      • Table 29-23. PST/DDATA Specification for MAC Instructions (continued)

        715
    • 29.7.2 Supervisor Instruction Set

      716
      • Table 29-24. PST/DDATA Specification for Supervisor-Mode Instructions

        716
  • 29.8 Motorola-Recommended BDM Pinout

    717
    • Figure 29-41. Recommended BDM Connector

      717
• Chapter 30 Chip Configuration Module (CCM)

  719
  • 30.1 Features

    719
  • 30.2 Modes of Operation

    719
    • 30.2.1 Master Mode

      720
    • 30.2.2 Single-Chip Mode

      720
  • 30.3 Block Diagram

    720
    • Figure 30-1. Chip Configuration Module Block Diagram

      720
  • 30.4 Signal Descriptions

    721
    • Table 30-1. Signal Properties

      721
    • 30.4.1 RCON

      721
    • 30.4.2 CLKMOD[1:0]

      721
    • 30.4.3 D[26:24, 21, 19:16] (Reset Configuration Override)

      721
  • 30.5 Memory Map and Registers

    721
    • 30.5.1 Programming Model

      721
      • Table 30-2. Write-Once Bits Read/Write Accessibility

        722
    • 30.5.2 Memory Map

      722
      • Table 30-3. Chip Configuration Module Memory Map

        722
    • 30.5.3 Register Descriptions

      723
      • 30.5.3.1 Chip Configuration Register (CCR)

        723
        • Figure 30-2. Chip Configuration Register (CCR)

          723
        • Table 30-4. CCR Field Descriptions (continued)

          723
      • 30.5.3.2 Reset Configuration Register (RCON)

        724
        • Figure 30-3. Reset Configuration Register (RCON)

          724
        • Table 30-5. RCON Field Descriptions (continued)

          724
        • Table 30-6. RCSC Chip Select Configuration

          725
        • Table 30-7. BOOTPS Port Size Configuration

          725
      • 30.5.3.3 Chip Identification Register (CIR)

        726
        • Figure 30-4. Chip Identification Register (CIR)

          726
        • Table 30-8. CIR Field Description

          726
  • 30.6 Functional Description

    726
    • 30.6.1 Reset Configuration

      726
      • Table 30-9. Reset Configuration Pin States During Reset

        727
      • Table 30-10. Configuration During Reset (continued)

        727
    • 30.6.2 Chip Mode Selection

      728
      • Table 30-11. Chip Configuration Mode Selection

        729
    • 30.6.3 Boot Device Selection

      729
    • 30.6.4 Output Pad Strength Configuration

      729
      • Table 30-12. Output Pad Driver Strength Selection

        729
    • 30.6.5 Clock Mode Selection

      729
      • Table 30-13. Clock Mode Selection

        730
    • 30.6.6 Chip Select Configuration

      730
  • 30.7 Reset

    730
  • 30.8 Interrupts

    730
• Chapter 31 IEEE 1149.1 Test Access Port (JTAG)

  731
  • Figure 31-1. JTAG Block Diagram

    732
  • 31.1 Features

    732
  • 31.2 Modes of Operation

    733
  • 31.3 External Signal Description

    733
    • 31.3.1 Detailed Signal Description

      733
      • Table 31-1. Signal Properties

        733
      • 31.3.1.1 JTAG_EN - JTAG Enable

        733
        • Table 31-2. Pin Function Selected

          733
        • Table 31-3. Signal State to the Disable Module

          734
      • 31.3.1.2 TCLK - Test Clock Input

        734
      • 31.3.1.3 TMS/BKPT - Test Mode Select / Breakpoint

        734
      • 31.3.1.4 TDI/DSI - Test Data Input / Development Serial Input

        734
      • 31.3.1.5 TRST/DSCLK - Test Reset / Development Serial Clock

        734
      • 31.3.1.6 TDO/DSO - Test Data Output / Development Serial Output

        735
  • 31.4 Memory Map/Register Definition

    735
    • 31.4.1 Memory Map

      735
    • 31.4.2 Register Descriptions

      735
      • 31.4.2.1 Instruction Shift Register (IR)

        735
      • 31.4.2.2 IDCODE Register

        735
        • Figure 31-2. IDCODE Register

          735
        • Table 31-4. IDCODE Register Field Descriptions

          736
      • 31.4.2.3 Bypass Register

        736
      • 31.4.2.4 JTAG_CFM_CLKDIV Register

        736
      • 31.4.2.5 TEST_CTRL Register

        736
      • 31.4.2.6 Boundary Scan Register

        736
  • 31.5 Functional Description

    737
    • 31.5.1 JTAG Module

      737
    • 31.5.2 TAP Controller

      737
      • Figure 31-3. TAP Controller State Machine Flow

        738
    • 31.5.3 JTAG Instructions

      738
      • Table 31-5. JTAG Instructions (continued)

        738
      • 31.5.3.1 External Test Instruction (EXTEST)

        739
      • 31.5.3.2 IDCODE Instruction

        739
      • 31.5.3.3 SAMPLE/PRELOAD Instruction

        739
      • 31.5.3.4 TEST_LEAKAGE Instruction

        740
      • 31.5.3.5 ENABLE_TEST_CTRL Instruction

        740
      • 31.5.3.6 HIGHZ Instruction

        740
      • 31.5.3.7 LOCKOUT_RECOVERY Instruction

        740
      • 31.5.3.8 CLAMP Instruction

        741
      • 31.5.3.9 BYPASS Instruction

        741
  • 31.6 Initialization/Application Information

    741
    • 31.6.1 Restrictions

      741
    • 31.6.2 Nonscan Chain Operation

      742
• Chapter 32 Mechanical Data

  743
  • 32.1 Pinout

    744
    • Figure 32-1. MCF5282 Pinout (256 MAPBGA)

      744
    • Table 32-1. MCF5282 Signal Description by Pin Number (Continued)

      745
    • Figure 32-2. 256 MAPBGA Package Dimensions

      749
  • 32.2 Ordering Information

    749
    • Table 32-2. Orderable Part Numbers

      749
• Chapter 33 Electrical Characteristics

  751
  • 33.1 Maximum Ratings

    751
    • Table 33-1. Absolute Maximum Ratings, (Continued)

      751
  • 33.2 Thermal Characteristics

    753
    • Table 33-2. Thermal Characteristics

      753
  • 33.3 DC Electrical Specifications

    754
    • Table 33-3. DC Electrical Specifications (Continued)

      754
  • 33.4 Phase Lock Loop Electrical Specifications

    756
    • Table 33-4. PLL Electrical Specifications

      756
  • 33.5 QADC Electrical Characteristics

    757
    • Table 33-5. QADC Absolute Maximum Ratings

      757
    • Table 33-6. QADC Electrical Specifications (Operating) (Continued)

      757
    • Table 33-7. QADC Conversion Specifications (Operating)

      759
  • 33.6 Flash Memory Characteristics

    759
    • Table 33-8. SGFM Flash Program and Erase Characteristics

      759
    • Table 33-9. SGFM Flash Module Life Characteristics

      760
  • 33.7 External Interface Timing Characteristics

    760
    • Table 33-10. Processor Bus Input Timing Specifications

      760
    • Figure 33-1. General Input Timing Requirements

      761
  • 33.8 Processor Bus Output Timing Specifications

    761
    • Table 33-11. External Bus Output Timing Specifications (Continued)

      761
    • Figure 33-2. Read/Write (Internally Terminated) Timing

      763
    • Figure 33-3. Read Bus Cycle Terminated by TA

      764
    • Figure 33-4. Read Bus Cycle Terminated by TEA

      765
    • Figure 33-5. SDRAM Read Cycle

      766
    • Table 33-12. SDRAM Timing

      766
    • Figure 33-6. SDRAM Write Cycle

      767
  • 33.9 General Purpose I/O Timing

    767
    • Table 33-13. GPIO Timing, (Continued)

      767
    • (VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V)

      767
    • Figure 33-7. GPIO Timing

      768
  • 33.10 Reset and Configuration Override Timing

    768
    • Table 33-14. Reset and Configuration Override Timing (Continued)

      768
    • Figure 33-8. RSTI and Configuration Override Timing

      769
  • 33.11 I2C Input/Output Timing Specifications

    769
    • Table 33-15. I2C Input Timing Specifications between SCL and SDA

      769
    • Table 33-16. I2C Output Timing Specifications between SCL and SDA

      770
    • Figure 33-9. I2C Input/Output Timings

      770
  • 33.12 Fast Ethernet AC Timing Specifications

    770
    • 33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)

      771
      • Table 33-17. MII Receive Signal Timing

        771
      • Figure 33-10. MII Receive Signal Timing Diagram

        771
    • 33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)

      771
      • Table 33-18. MII Transmit Signal Timing

        772
      • Figure 33-11. MII Transmit Signal Timing Diagram

        772
    • 33.12.3 MII Async Inputs Signal Timing (ECRS and ECOL)

      772
      • Table 33-19. MII Async Inputs Signal Timing

        772
      • Figure 33-12. MII Async Inputs Timing Diagram

        772
    • 33.12.4 MII Serial Management Channel Timing (EMDIO and EMDC)

      773
      • Table 33-20. MII Serial Management Channel Timing

        773
      • Figure 33-13. MII Serial Management Channel Timing Diagram

        773
  • 33.13 DMA Timer Module AC Timing Specifications

    774
    • Table 33-21. Timer Module AC Timing Specifications

      774
  • 33.14 QSPI Electrical Specifications

    774
    • Table 33-22. QSPI Modules AC Timing Specifications

      774
    • Figure 33-14. QSPI Timing

      774
  • 33.15 JTAG and Boundary Scan Timing

    775
    • Table 33-23. JTAG and Boundary Scan Timing

      775
    • Figure 33-15. Test Clock Input Timing

      775
    • Figure 33-16. Boundary Scan (JTAG) Timing

      776
    • Figure 33-17. Test Access Port Timing

      776
    • Figure 33-18. TRST Timing

      776
    • Figure 33-19. BKPT Timing

      777
  • 33.16 Debug AC Timing Specifications

    777
    • Table 33-24. Debug AC Timing Specification

      777
    • Figure 33-20. Real-Time Trace AC Timing

      778
    • Figure 33-21. BDM Serial Port AC Timing

      778
• Appendix A Register Memory Map

  779
  • Table A-1. CPU Space Register Memory Map

    779
  • Table A-2. Module Memory Map Overview

    780
  • Table A-3. Register Memory Map (Continued)

    781