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MCF5282 User’s Manual
MOTOROLA
 
EMAC Instruction Set Summary  
Figure 3-9. Two’s Complement, Signed Fractional Equation
This format can represent numbers in the range -1 < operand < 1 - 2
(N-1)
.
For words and longwords, the largest negative number that can be represented is -1, whose
internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word
is 0x7FFF or (1 - 2
-15
); the most positive longword is 0x7FFF_FFFF or (1 - 2
-31
).
3.5.3
MAC Opcodes
MAC opcodes are described in the ColdFire Programmer’s Reference Manual
Note the following:
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final 
operation that involves the product and the accumulator.
• The overflow (V) flag is handled differently. It is set if the complete product cannot 
be represented as a 40-bit value (this applies to 32x32 integer operations only) or if 
the combination of the product with an accumulator cannot be represented in the 
given number of bits. The EMAC design includes an additional 
product/accumulation overflow bit for each accumulator that are treated as sticky 
indicators and are used to calculate the V bit on each MAC or MSAC instruction. 
See Section 3.4.1, “MAC Status Register (MACSR).”
• For the MAC design, the assembler syntax of the MAC (multiply and add to 
accumulator) and MSAC (multiply and subtract from accumulator) instructions 
does not include a reference to the single accumulator. For the EMAC, it is expected 
that assemblers support this syntax and that no explicit reference to an accumulator 
is interpreted as a reference to ACC0. These assemblers would also support syntaxes 
where the destination accumulator is explicitly defined.
• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, 
where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed 
before the product is added to or subtracted from the accumulator. Without this 
operator, the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I] 
is set), SF is ignored and no shift is performed. Because a product can overflow, the 
following guidelines are implemented:
value
1 a
N 1
(
)
2
i 1 N
+
(
)
ai
i
0
=
N 2
+
=