Motorola MCF5281 用户手册
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Chapter 4. Cache
4-5
Cache Operation
4.3.4
Reset
A hardware reset clears the CACR and disables the cache. The contents of the tag array are
not affected by the reset. Accordingly, the system startup code must explicitly perform a
cache invalidation by setting CACR[24] before the cache can be enabled.
not affected by the reset. Accordingly, the system startup code must explicitly perform a
cache invalidation by setting CACR[24] before the cache can be enabled.
4.3.5
Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 4.2, “Cache Physical Organization,” the cache hardware includes
a 16-byte line-fill buffer for providing temporary storage for the last fetched line.
a 16-byte line-fill buffer for providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in both
the tag memory and the line-fill buffer generates an external fetch. For data misses, the size
of the external fetch is always 16 bytes. For instruction misses, the size of the external fetch
is determined by the value contained in the 2-bit CLNF field of the CACR and the miss
address. Table 4-1 shows the relationship between the CLNF bits, the miss address, and the
size of the external fetch.
the tag memory and the line-fill buffer generates an external fetch. For data misses, the size
of the external fetch is always 16 bytes. For instruction misses, the size of the external fetch
is determined by the value contained in the 2-bit CLNF field of the CACR and the miss
address. Table 4-1 shows the relationship between the CLNF bits, the miss address, and the
size of the external fetch.
Depending on the runtime characteristics of the application and the memory response
speed, overall performance may be increased by programming the CLNF bits to values {00,
01}.
speed, overall performance may be increased by programming the CLNF bits to values {00,
01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss
address is accessed first followed by the remaining three longwords that are accessed by
incrementing the longword address in a modulo-16 fashion as shown below:
address is accessed first followed by the remaining three longwords that are accessed by
incrementing the longword address in a modulo-16 fashion as shown below:
if miss address[3:2] = 00
fetch sequence = {0x0, 0x4, 0x8, 0xC}
if miss address[3:2] = 01
fetch sequence = {0x4, 0x8, 0xC, 0x0}
if miss address[3:2] = 10
fetch sequence = {0x8, 0xC, 0x0, 0x4}
if miss address[3:2] = 11
fetch sequence = {0xC, 0x0, 0x4, 0x8}
Table 4-1. Initial Fetch Offset vs. CLNF Bits
CLNF[1:0]
Longword Address Bits
00
01
10
11
00
Line
Line
Line
Longword
01
Line
Line
Longword
Longword
1X
Line
Line
Line
Line