Motorola MCF5281 用户手册
4-12
MCF5282 User’s Manual
MOTOROLA
Cache Programming Model
14–13
SM
Supervisor mode. This two-bit field allows the given ACR to be applied to references based on
operating privilege mode of the ColdFire processor. The field uses the ACR for user references only,
supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
operating privilege mode of the ColdFire processor. The field uses the ACR for user references only,
supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
12–7
—
Reserved, should be cleared.
6
CM
Cache mode. This bit defines the cache mode: 0 is cacheable, 1 is noncacheable.
0 Caching enabled
1 Caching disabled
0 Caching enabled
1 Caching disabled
5
BWE
Buffered write enable. This bit defines the value for enabling buffered writes. If BWE = 0, the
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle
is completed. If BWE = 1, the write cycle on the local bus is terminated immediately and the operation
is then buffered in the bus controller. In this mode, operand write cycles are effectively decoupled
between the processor's local bus and the external bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access
errors may be more difficult. For the V2 ColdFire CPU, the reporting of access errors on operand writes
is always imprecise, and enabling buffered writes simply decouples the write instruction from the
signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle
is completed. If BWE = 1, the write cycle on the local bus is terminated immediately and the operation
is then buffered in the bus controller. In this mode, operand write cycles are effectively decoupled
between the processor's local bus and the external bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access
errors may be more difficult. For the V2 ColdFire CPU, the reporting of access errors on operand writes
is always imprecise, and enabling buffered writes simply decouples the write instruction from the
signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
4–3
—
Reserved, should be cleared.
2
WP
Write protect. The WP bit defines the write-protection attribute. If the effective memory attributes for a
given access select the WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
given access select the WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
1–0
—
Reserved, should be cleared.
Table 4-8. ACR Field Descriptions (continued)
Bits
Name
Description