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Chapter 8. System Control Module (SCM)
8-3
Register Descriptions
8.4
Register Descriptions
8.4.1
Internal Peripheral System Base Address Register
(IPSBAR)
(IPSBAR)
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the
on-chip peripherals. At reset, the base address is loaded with a default location of
0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space
associated with the internal modules can be moved by loading a different value into the
IPSBAR at a later time.
on-chip peripherals. At reset, the base address is loaded with a default location of
0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space
associated with the internal modules can be moved by loading a different value into the
IPSBAR at a later time.
NOTE
Accessing reserved IPSBAR memory space could result in an
unterminated bus cycle that causes the core to hang. Only a
hard reset will allow the core to recover from this state.
Therefore, all bus accesses to IPSBAR space should fall within
a module’s memory map space.
unterminated bus cycle that causes the core to hang. Only a
hard reset will allow the core to recover from this state.
Therefore, all bus accesses to IPSBAR space should fall within
a module’s memory map space.
If an address “hits” in overlapping memory regions, the following priority is used to
determine what memory is accessed:
determine what memory is accessed:
1. IPSBAR
2. RAMBAR
3. Cache
4. SDRAM
5. Chip Selects
2. RAMBAR
3. Cache
4. SDRAM
5. Chip Selects
NOTE
This is the list of memory access priorities when viewed from
the processor core.
the processor core.
See Figure 8-1 and Table 8-2 for descriptions of the bits in IPSBAR.