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Chapter 9.  Clock Module  

9-11

 

XTAL must be tied low in external clock mode when reset is
asserted. If it is not, clocks could be suspended indefinitely.

The external clock is divided by two internally to produce the system clocks.

In external clock mode, the system is static and does not recognize reset until a clock is
applied to EXTAL.

In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input
reference clock to the PLL begins operating within the limits given in the electrical
specifications.

If a PLL failure causes a reset, the system enters reset using the reference clock. Then the
system clock source changes to the PLL operating in SCM. If SCM is not functional, the
system becomes static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL
fails, the system becomes static. If external reset is asserted, the system cannot enter reset
unless the PLL is capable of operating in SCM.

In normal PLL clock mode, the default system frequency is two times the reference
frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency
multiplier. 

When programming the PLL, do not exceed the maximum system clock frequency listed in
the electrical specifications. Use this procedure to accommodate the frequency overshoot
that occurs when the MFD bits are changed:

1. Determine the appropriate value for the MFD and RFD fields in the SYNCR. The 

amount of jitter in the system clocks can be minimized by selecting the maximum 
MFD factor that can be paired with an RFD factor to provide the required frequency.

2. Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR.

1

f

ref

 = input reference frequency

f

sys

 = CLKOUT frequency

MFD ranges from 0 to 7.
RFD ranges from 0 to 7.

Normal PLL clock mode

f

sys

 = f

ref

 

× 2(MFD + 2)/2

RFD

1:1 PLL clock mode

f

sys

 = f

ref

External clock mode

f

sys

 = f

ref