Motorola MCF5281 用户手册
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Chapter 10. Interrupt Controller Modules
10-9
Register Descriptions
10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism
to allow software generation of interrupts for each possible source for functional or debug
purposes. The system design may reserve one or more sources to allow software to
self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate
request) in the appropriate INTFRCn register. The assertion of an interrupt request via the
INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is
cleared by reset.
to allow software generation of interrupts for each possible source for functional or debug
purposes. The system design may reserve one or more sources to allow software to
self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate
request) in the appropriate INTFRCn register. The assertion of an interrupt request via the
INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is
cleared by reset.
Table 10-7. IMRLn Field Descriptions
Bits
Name
Description
31–1
INT_MASK
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding
IMRLn bit determines whether an interrupt condition can generate an interrupt.
The corresponding IPRLn bit reflects the state of the interrupt signal even if the
corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
IMRLn bit determines whether an interrupt condition can generate an interrupt.
The corresponding IPRLn bit reflects the state of the interrupt signal even if the
corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
0
MASKALL
Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and
IMRLn to ones, disabling all interrupt sources, and providing a global mask-all
capability.
IMRLn to ones, disabling all interrupt sources, and providing a global mask-all
capability.
31
16
Field
INTFRCH[63:48]
Reset
0000_0000_0000_0000
R/W
R/W
15
0
Field
INTFRCH[47:32]
Reset
0000_0000_0000_0000
R/W
R/W
IPSBAR + 0xC10, 0xD10
Figure 10-5. Interrupt Force Register High (INTFRCHn)
Table 10-8. INTFRCHn Field Descriptions
Bits
Name
Description
31–0
INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or
debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source