Motorola MCF5281 用户手册
MOTOROLA
Chapter 13. External Interface Module (EIM)
13-3
Data Transfer Operation
The address bus, write data, TS, and all attribute signals change on the rising edge of
CLKOUT. Read data is latched into the MCF5282 on the rising edge of CLKOUT.
CLKOUT. Read data is latched into the MCF5282 on the rising edge of CLKOUT.
The MCF5282 bus supports byte, word, and longword operand transfers and allows
accesses to 8-, 16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the
number of wait states for the external slave being accessed, and whether internal transfer
termination is enabled, can be programmed in the chip-select control registers (CSCRs) and
the DRAM control registers (DACRs).
accesses to 8-, 16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the
number of wait states for the external slave being accessed, and whether internal transfer
termination is enabled, can be programmed in the chip-select control registers (CSCRs) and
the DRAM control registers (DACRs).
Figure 13-2 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit
memory should be connected to D[31:24] (BS3). A longword transfer takes four transfers
on D[31:24], starting with the MSB and going to the LSB.
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit
memory should be connected to D[31:24] (BS3). A longword transfer takes four transfers
on D[31:24], starting with the MSB and going to the LSB.
Figure 13-2. Connections for External Memory Port Sizes
The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable
(OE) with respect to CLKOUT is similar in that all transitions occur during the low phase
of CLKOUT. However, due to differences in on-chip signal routing, signals may not assert
simultaneously.
(OE) with respect to CLKOUT is similar in that all transitions occur during the low phase
of CLKOUT. However, due to differences in on-chip signal routing, signals may not assert
simultaneously.
Figure 13-3. Chip-Select Module Output Timing Diagram
13.4.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5282 first compares the address of that bus cycle
with the base address and mask configurations programmed for chip selects 0–7
with the base address and mask configurations programmed for chip selects 0–7
Processor
Data Bus
Byte 0
8-Bit Port
16-Bit Port
32-Bit Port
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
D[31:24]
D[23:16]
D[15:8]
D[7:0]
External
Memory
Memory
Memory
Byte Enable
BS3
BS2
BS1
BS0
Driven with
indeterminate values
Driven with
indeterminate values
CS[7:0]
CLKOUT
BS[3:0]
OE