Motorola MCF5281 用户手册
14-2
MCF5282 User’s Manual
MOTOROLA
Overview
Figure 14-1. MCF5282 Block Diagram with Signal Interfaces
TDO/DSO
TDI/DSI
TMS/BKPT
TCLK
Interface
Chip
UART1
Serial
I/O
EXTAL
DTIN
[3
:0
]
D
T
O
U
T
[3:
0]
TA
R/W
SIZ[1:0]
D[31:0]
A[23:0]
JTAG
Port
Selects
ColdFire V2 Core
EMAC
External
UTxD0
URxD0
UR
T
S
0
UC
TS
0
UTxD1
URxD1
UR
T
S
1
UC
TS
1
DRAMW
2
24
32
BS[3:0]
CS[6:0]
7
4
2
TEA
TRST/DSCLK
TEST
4
4
Test
Controller
OE
SRAS
SCAS
SCKE
SCAS
SCKE
TS
4
P
S
T
[3
:0
]
4
TIP
I
2
C
Module
SC
L
SD
A
UART2
Serial
I/O
DMA
Timer
Modules
DRAM
Controller
2-Kbyte
DDATA[3:0]
D-Cache/I-Cache
Debug Module
DIV
Clock Module
Chip
Configuration
Reset
Controller
Po
wer
RCON
CLKMOD0
CLKMOD1
RSTI
RSTO
(PLL)
Edgeport
Interrupt
Controller 0
Interrupt
Controller 1
IRQ[7:1]
FEC
UART0
Serial
I/O
DMA
Controlle
r
Watchdog
Timer
General
Purpose
Timer A
General
Purpose
Timer B
QSPI
FlexCAN
QADC
PIT
Timers
(PIT0–
(PIT0–
JTAG_EN
CLKOUT
XTAL
ETXCLK
ETXEN
ETXDO
ECOL
ERXCLK
ERXDV
ERXD0
ECRS
ETXD[3:1]
ETXER
ERXD[3:1]
ERXER
EMDIO
EMDC
UTxD2
URxD2
(DTIM0–
DTIM3)
VR
E
F
H
VREFL
AN
0/
AN
W
AN1/
ANX
AN2/
ANY
AN
3
/A
N
Z
AN52/
MA0
AN53/
MA1
AN
55
/T
R
IG
1
AN
56
/T
R
IG
2
SYNCA
G
P
TA
[3
:0
]
4
GP
T
B
[3:
0
]
4
SYNCB
Q
SPI
_DI
N
QSP
I_
D
O
U
T
Q
SPI
_CLK
Q
SPI
_CS[
3:
0]
CA
N
T
X
CANRX
Mana
gemen
t
Module
Ports
Module
SDRAM_CS[1:0]
PIT3)
In
te
rnal
Bu
s
Arb
ite
r
Sy
st
em
Cont
rol
Module
(S
CM)
VDDF
VSTBY
Flash
Module
64K
SRAM