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Chapter 14.  Signal Descriptions  

14-23

These inputs are the external interrupt sources. See Chapter 11, “Edge Port Module
(EPORT)” for more information on these interrupt sources and their corresponding
registers.

These pins are configured as GPIO PNQ[7:1] in single-chip mode.

The following signals are used by the Ethernet module for data and clock signals.

The bidirectional EMDIO signal transfers control information between the external PHY
and the media-access controller. Data is synchronous to EMDC and applies to MII mode
operation. This signal is an input after reset. When the FEC is operated in 10 Mbps 7-wire
interface mode, this signal should be connected to VSS. 

This pin can also be configured as GPIO PAS5 or URXD2.

EMDC is an output clock which provides a timing reference to the PHY for data transfers
on the EMDIO signal and applies to MII mode operation.  

This pin can also be configured as GPIO PAS4 or UTXD2.

This is an input clock which provides a timing reference for ETXEN, ETXD[3:0] and
ETXER.  

This pin can also be configured as GPIO PEH7.

The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII.
This signal is asserted with the first nibble of a preamble and is negated before the first
ETXCLK following the final nibble of the frame.  

This pin can also be configured as GPIO PEH6.

ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN.
This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode data
in conjunction with ETXD[3:1].