Motorola MCF5281 用户手册
MOTOROLA
Chapter 15. Synchronous DRAM Controller Module
15-23
SDRAM Example
15.3.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register
setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the
corresponding MCF5282 address pins must be determined while being aware of masking
requirements.
setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the
corresponding MCF5282 address pins must be determined while being aware of masking
requirements.
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how
DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before
the mode register bit is set, DMR0[19] must be set to enable masking.
DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before
the mode register bit is set, DMR0[19] must be set to enable masking.
Table 15-30. Mode Register Initialization
MCF5282 Pins
SDRAM Pins
Mode Register Initialization
A20
A10
Reserved
X
A19
A9
WB
0
A18
A8
Opmode
0
A17
A7
Opmode
0
A9
A6
CASL
0
A10
A5
CASL
0
A11
A4
CASL
1
A12
A3
BT
0
A13
A2
BL
0
A14
A1
BL
0
A15
A0
BL
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Setting
xxxx_xxxx_xxxx_000x
(hex)
0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
V
Setting
0000_100x_xxxx_xxxx
(hex)
0800
Table 15-31. Mode Register Mapping to MCF5282 A[31:0]