Motorola MCF5281 用户手册
16-2
MCF5282 User’s Manual
MOTOROLA
Overview
Figure 16-1. DMA Signal Diagram
NOTE
Throughout this chapter “external request” and DREQ are used
to refer to a DMA request from one of the on-chip UARTS or
DMA timers. For details on the connections associated with
DMA request inputs, see Section 16.2, “DMA Request Control
(DMAREQC).”
to refer to a DMA request from one of the on-chip UARTS or
DMA timers. For details on the connections associated with
DMA request inputs, see Section 16.2, “DMA Request Control
(DMAREQC).”
16.1.1 DMA Module Features
The DMA controller module features are as follows:
• Four independently programmable DMA controller channels
• Auto-alignment feature for source or destination accesses
• Dual-address transfers
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Auto-alignment feature for source or destination accesses
• Dual-address transfers
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
MUX
Arbitration/
Bus Interface
Data Path
Control
Internal
External
Channel
Channel
MUX
Registered
Data Path
SAR0
DAR0
DAR0
BCR0
DCR0
DSR0
DCR0
DSR0
Channel 0
Interrupts
SAR1
DAR1
BCR1
DAR1
BCR1
DCR1
DSR1
Channel 1
SAR2
DAR2
BCR2
DAR2
BCR2
DCR2
DSR2
Channel 2
SAR3
DAR3
BCR3
DAR3
BCR3
DCR3
DSR3
DSR3
Channel 3
Bus
Requests
Attributes
Current Master Attributes
Write Data Bus
Read Data Bus
System Bus Address
System Bus Size
System Bus Size
Channel
Enables
Requests
Bus Signals
Control
Control