Motorola MCF5281 用户手册
17-4
MCF5282 User’s Manual
MOTOROLA
FEC Top-Level Functional Diagram
17.3 FEC Top-Level Functional Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a
combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant
with industry and IEEE 802.3 standards.
combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant
with industry and IEEE 802.3 standards.
Figure 17-1. FEC Block Diagram
The descriptor controller is a RISC-based controller that provides the following functions
in the FEC:
in the FEC:
• Initialization (those internal registers not initialized by the user or hardware)
• High level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
• High level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
SIF
CSR
FIFO
DMA
Descriptor
Controller
MII
Receive
Transmit
Bus
Controller
Controller
EMDC
EMDIO
ERXCLK
ERXDV
ERXD[3:0]
ERXER
ERXDV
ERXD[3:0]
ERXER
ETCLK
ETXEN
ETXD[3:0]
ETXER
ETXD[3:0]
ETXER
ECRS,ECOL
MIB
(RISC +
microcode)
I/O
PAD
MDO
MDEN
MDI
Counters
MII/7-WIRE DATA
OPTION
RAM
RAM I/F
FEC Bus