Motorola MCF5281 用户手册

MOTOROLA

Chapter 17.  Fast Ethernet Controller (FEC)  

17-19

Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To
signify a good self-test, the transceiver indicates a collision to the FEC within 4
microseconds after completion of a frame transmitted by the Ethernet controller. This
indication of a collision does not imply a real collision error on the network, but is rather
an indication that the transceiver still seems to be functioning properly. This is called the
heartbeat condition. 

If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the
FEC after a frame transmission, then a heartbeat error occurs. When this error occurs, the
FEC closes the buffer, sets the HB bit in the EIR register, and generates the HBERR
interrupt if it is enabled.

If the receive block has data to put into the receive FIFO and the receive FIFO is full, the
FEC sets the OV bit in the RxBD. All subsequent data in the frame will be discarded and
subsequent frames may also be discarded until the receive FIFO is serviced by the DMA
and space is made available. At this point the receive frame/status word is written into the
FIFO with the OV bit set. This frame must be discarded by the driver.

The Ethernet controller handles up to seven dribbling bits when the receive frame
terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC
calculation. If there is a CRC error, then the frame non-octet aligned (NO) error is reported
in the RxBD. If there is no CRC error, then no error is reported.

When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR
bit in the RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if
checking is not required.

When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be
generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated
unless the frame length exceeds 2047 bytes).