Motorola MCF5281 用户手册
17-40
MCF5282 User’s Manual
MOTOROLA
Programming Model
17.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 2-bit read/write register programmed by the user to control the amount of
data required in the transmit FIFO before transmission of a frame can begin. This allows
the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency
(TFWR = 11) due to contention for the system bus. Setting the watermark to a high value
will minimize the risk of transmit FIFO underrun due to contention for the system bus. The
byte counts associated with the TFWR field may need to be modified to match a given
system requirement (worst case bus access latency by the transmit data DMA channel).
data required in the transmit FIFO before transmission of a frame can begin. This allows
the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency
(TFWR = 11) due to contention for the system bus. Setting the watermark to a high value
will minimize the risk of transmit FIFO underrun due to contention for the system bus. The
byte counts associated with the TFWR field may need to be modified to match a given
system requirement (worst case bus access latency by the transmit data DMA channel).
31
16
Field
GADDR2
Reset
Uninitialized
R/W
R/W
15
0
Field
GADDR2
Reset
Uninitialized
R/W
R/W
Address
IPSBAR + 0x1124
Figure 17-20. Descriptor Group Lower Address Register (GALR)
Table 17-29. GALR Field Descriptions
Bits
Name
Description
31–0
GADDR2
The GADDR2 register contains the lower 32 bits of the 64-bit
hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR2
contains hash index bit 31. Bit 0 of GADDR2 contains hash
index bit 0.
hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR2
contains hash index bit 31. Bit 0 of GADDR2 contains hash
index bit 0.
31
16
Field
—
Reset
0000_0000_0000_0000
R/W
R/W
15
2
1
0
Field
—
X_WMRK
Reset
0000_0000_0000_0000
R/W
R/W
Address
IPSBAR + 0x1144
Figure 17-21. FIFO Transmit FIFO Watermark Register (TFWR)