Motorola MCF5281 用户手册
MOTOROLA
Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3)
19-3
Memory Map and Registers
19.5 Memory Map and Registers
This subsection describes the memory map and register structure for PIT0–PIT3.
19.5.1 Memory Map
This device has four programmable interrupt timers with the following IPSBAR offset for
base address locations for each timer.
base address locations for each timer.
PIT0: 0x0015_0000
PIT1: 0x0016_0000
PIT2: 0x0017_0000
PIT3: 0x0018_0000
19.5.2 Registers
The PIT programming model consists of these registers:
• The PIT control and status register (PCSR) configures the timer’s operation.
• The PIT modulus register (PMR) determines the timer modulus reload value.
• The PIT count register (PCNTR) provides visibility to the counter value.
• The PIT modulus register (PMR) determines the timer modulus reload value.
• The PIT count register (PCNTR) provides visibility to the counter value.
Table 19-2. Programmable Interrupt Timer Modules Memory Map
IPSBAR Offset
for PITx
Address
Bits 15–8
Bits 7–0
Access
1
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
only addresses have no effect and result in a cycle termination transfer error.
only addresses have no effect and result in a cycle termination transfer error.
0x001x_0000
PIT Control and Status Register (PCSR)
S
0x001x_0002
PIT Modulus Register (PMR)
S
0x001x_0004
PIT Count Register (PCNTR)
S/U
0x001x_0006
Unimplemented
2
2
Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
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