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Chapter 21.  DMA Timers (DTIM0–DTIM3)  

21-1

This chapter describes the configuration and operation of the four Direct Memory Access
(DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers
provide input capture and reference compare capabilities with optional signaling of events
using interrupts or triggers. Additionally, programming examples are included.

The designation “n” is used throughout this section to refer to
registers or signals associated with one of the four identical
timer modules—DTIM0, DTIM1, DTIM2, or DTIM3.

Each DMA timer module has a separate register set for configuration and control. The
timers can be configured to operate from the system clock or from an external clocking
source using the DTINn signal. If the system clock is selected, it can be divided by 16 or 1.
The selected clock source is routed to an 8-bit programmable prescaler that clocks the
actual DMA timer counter register (DTCNn). Using the DTMRn, DTXMRn, DTCRn, and
DTRRn registers, the DMA timer may be configured to assert an output signal, generate an
interrupt, or initiate a DMA transfer on a particular event.

Figure 21-1 is a block diagram of one of the four identical timer modules.