Motorola MCF5281 用户手册

21-8

MOTOROLA

 

21.2.11  DMA Timer Counters (DTCNn)

The current value of the 32-bit DTCNs can be read at anytime without affecting counting.
Writing to DTCNn, shown in Figure 21-7, clears it. The timer counter increments on the
clock source rising edge (system clock ÷ 1, system clock ÷ 16, or DTINn). 

The general-purpose timer modules are typically used in the following manner, though this
is not necessarily the program order in which these actions must occur:

• The  DTMRn and DTXMRn registers are configured for the desired function and 

behavior.
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTINn
— Configure DTOUTn output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture 

edge

• The  DTMRn[CLK] register is configured to select the clock source to be routed to 

the prescaler.
— System clock (can be divided by 1 or 16)
— DTINn, the maximum value of DTINn is 1/5 of the system clock, as described 

in the MCF5282MCF523x Electrical Characteristics. 

31

0

Field

CAP (32-bit capture counter value) 

Reset

0000_0000_0000_0000_0000_0000_0000_0000

R/W

R

Address

IPSBAR + 0x408 (DTCR0); + 0x448 (DTCR1); + 0x488 (DTCR2); + 0x4C8 (DTCR3) 

Figure 21-6. DTCRn Bit Definitions

31

0

Field

 32-bit timer counter value count

Reset

0000_0000_0000_0000_0000_0000_0000_0000

R/W

R/W (to reset)

Address

IPSBAR + 0x40C (DTCN0); + 0x44C (DTCN1); + 0x48C (DTCN2); + 0x4CC (DTCN3)

Figure 21-7. DTCNn Bit Definitions