Motorola MCF5281 用户手册

22-10

MOTOROLA

 

The QMR, shown in Figure 22-3, determines the basic operating modes of the QSPI
module. Parameters such as QSPI_CLK polarity and phase, baud rate, master mode
operation, and transfer size are determined by this register. The data output high impedance
enable, DOHIE, controls the operation of QSPI_Dout between data transfers. When
DOHIE is cleared, QSPI_Dout is actively driven between transfers. When DOHIE is set,
QSPI_Dout assumes a high impedance state.

Because the QSPI does not operate in slave mode, the master
mode enable bit, QMR[MSTR], must be set for the QSPI
module to operate correctly.

15

14

13

10

9

8

7

0

Field MSTR DOHIE

BITS

CPOL CPHA

BAUD

Reset

0000_0001_0000_0100

R/W

R/W

Address

IPSBAR + 0x340

15

MSTR

Master mode enable. 
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.

14

DOHIE

Data output high impedance enable. Selects QSPI_Dout mode of operation.
0 Default value after reset. QSPI_Dout is actively driven between transfers.
1 QSPI_Dout is high impedance between transfers.

13–10

BITS

Transfer size. Determines the number of bits to be transferred for each entry in the queue. 
Value Bits per transfer
0000 16
0001– 0111 Reserved
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15

9

CPOL

Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.