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Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
22-17
Programming Model
3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any
interrupts.
4. Write QAR with 0x0020 to select the first command RAM entry.
5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00,
5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00,
0x7D00, 0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and
0x7700 to set up four transfers for each chip select. The chip selects are active low
in this example.
0x7700 to set up four transfers for each chip select. The chip selects are active low
in this example.
6. Write QAR with 0x0000 to select the first transmit RAM entry.
7. Write QDR with sixteen 12-bit words of data.
8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry
7. Write QDR with sixteen 12-bit words of data.
8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry
15.
9. Set QDLYR[SPE] to enable the transfers.
10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are
10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are
complete.
11. Write QAR with 0x0010 to select the first receive RAM entry.
12. Read QDR to get the received data for each transfer.
13. Repeat steps 5 through 13 to do another transfer.
12. Read QDR to get the received data for each transfer.
13. Repeat steps 5 through 13 to do another transfer.