Motorola MCF5281 用户手册
23-8
MCF5282 User’s Manual
MOTOROLA
Register Descriptions
23.3.4 UART Clock Select Registers (UCSRn)
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled
system clock as the clocking source for the transmitter and receiver. See Section 23.5.1,
“Transmitter/Receiver Clock Source.” The transmitter and receiver can use different clock
sources. To use the system clock for both, set UCSRn to 0xDD.
system clock as the clocking source for the transmitter and receiver. See Section 23.5.1,
“Transmitter/Receiver Clock Source.” The transmitter and receiver can use different clock
sources. To use the system clock for both, set UCSRn to 0xDD.
Table 23-5 describes UCSRn fields.
5
PE
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with
incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received address or data (A/D) bit. PE is
valid only when RxRDY = 1.
valid only when RxRDY = 1.
4
OE
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character
when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position.
When this occurs, the character in the receiver shift register and its break detect, framing error status, and
parity error, if any, are lost. OE is cleared by the
When this occurs, the character in the receiver shift register and its break detect, framing error status, and
parity error, if any, are lost. OE is cleared by the
RESET
ERROR
STATUS
command in UCRn.
3
TxEMP Transmitter empty.
0 The transmit buffer is not empty. Either a character is being shifted out, or the transmitter is disabled. The
transmitter is enabled/disabled by programming UCRn[TC].
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty).
This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter
holding register awaiting transmission.
holding register awaiting transmission.
2
TxRDY Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent
to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled,
characters loaded into the transmitter holding register are not sent.
characters loaded into the transmitter holding register are not sent.
1
FFULL FIFO full.
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full
are lost.
0
RxRDY Receiver ready.
0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
1 One or more characters were received and are waiting in the receive buffer FIFO.
7
4
3
0
Field
RCS
TCS
Reset
0000_0000
R/W
Write only
Address
IPSBAR + 0x204 (UCSR0), 0x244 (UCSR1), 0x284 (UCSR2)
Figure 23-5. UART Clock Select Register (UCSRn)
Table 23-4. USRn Field Descriptions (continued)
Bits
Name
Description