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Chapter 25.  FlexCAN  
25-19
Functional Overview
• If the FlexCAN is in debug mode when the STOP bit is set, the FlexCAN will 
assume that debug mode should be exited. As a result, it will try to synchronize with 
the CAN bus, and only then will it await the conditions required for entry into 
low-power stop mode.
• Unlike other modules, the FlexCAN does not come out of reset in low-power stop 
mode. The basic FlexCAN initialization procedure (see Section 25.4.10, “FlexCAN 
Initialization Sequence”
) should be executed before placing the module in 
low-power stop mode.
• If the FlexCAN is in low-power stop mode with the self-wake mechanism engaged 
and is operating with a single system clock per time quantum, there can be extreme 
cases in which FlexCAN wake-up on recessive to dominant edge may not conform 
to the CAN protocol. FlexCAN synchronization will be shifted one time quantum 
from the wake-up event. This shift lasts until the next recessive to dominant edge, 
which resynchronizes the FlexCAN to be in conformance with the CAN protocol. 
The same holds true when the FlexCAN is in auto-power save mode and awakens 
on a recessive to dominant edge.
25.4.11.3  Auto-Power Save Mode
Auto-power save mode enables normal operation with optimized power savings. Once the
auto-power save (APS) bit in CANMCR is set, the FlexCAN looks for a set of conditions
in which there is no need for its clocks to be running. If these conditions are met, the
FlexCAN stops its clocks, thus saving power. The following conditions will activate
auto-power save mode.
• No Rx/Tx frame in progress.
• No transfer of Rx/Tx frames to and from an SMB, and no Tx frame awaiting 
transmission in any message buffer.
• No CPU access to the FlexCAN module.
• The FlexCAN is not in debug mode, low-power stop mode, or the bus off state.
While its clocks are stopped, if the FlexCAN senses that any one of the aforementioned
conditions is no longer true, it restarts its clocks. The FlexCAN then continues to monitor
these conditions and stops/restarts its clocks accordingly.
25.4.12  Interrupts
The module can generate up to 19 interrupt sources (16 interrupts due to message buffers
and 3 interrupts due to Bus-off, Error and Wake-up). Each one of the message buffers can
be an interrupt source, if its corresponding IMASK bit is set. 
There is no distinction between Tx and Rx interrupts for a particular buffer, under the
assumption that the buffer is initialized for either transmission or reception, and thus its