Motorola MCF5281 用户手册

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Chapter 25.  FlexCAN  
25-25
Programmer’s Model
25.5.5 FlexCAN Control Register 2 (CANCTRL2)
 
Table 25-13 describes the CANCTRL2 fields.
Table 25-12. PRESDIV Field Descriptions
Bits
Name
Description
7–0
PRES_DIV Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency and 
the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency 
as the system clock. The valid programmed values are 0 through 255. See Section 25.4.8, “Bit 
Timing” for more information.
7
6
5
3
2
0
Field
RJW
PSEG1
PSEG2
Reset
0000_0000
R/W
R/W
Address
IPSBAR + 0x1C_0009
Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)
Table 25-13. CANCTRL2 Field Descriptions
Bits
Name
Description
7–6
RJW Resynchronization jump width. The RJW field defines the maximum number of time quanta a bit time 
may be changed during resynchronization. The valid programmed values are 0 through 3.
The resynchronization jump width is calculated as follows:
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
5–3
PSEG1 PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer segment 
1 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 1 is calculated as follows:
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
2–0
PSEG2 PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer segment 2 in 
the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 2 is calculated as follows:
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
S-clock
fsys
2 PRESDIV + 1
(
)
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