Motorola MCF5281 用户手册

25-30

MOTOROLA

 

IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which
buffer will generate an interrupt after a successful transmission/reception (that is, when the
corresponding IFLAG bit is set).

The interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0
(IMASK_L). The register can be accessed by the master as a 16-bit register, or each byte
can be accessed individually using an 8-bit (byte) access cycle.

Table 25-18 describes the IMASK fields.

3

—

Reserved, should be cleared.

2

BOFFINT Bus off interrupt. The BOFFINT bit is used to request an interrupt when the FlexCAN enters 

the bus off state.
0 No bus off interrupt requested.
1 When the FlexCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in 

CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after 
reset.

1

ERRINT

Error interrupt. The ERRINT bit is used to request an interrupt when the FlexCAN detects a 
transmit or receive error.
0 No error interrupt request.
1 If an event which causes one of the error bits in the error and status register to be set 

occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt 
request is generated.

To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.

0

WAKEINT Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the 

FlexCAN module is in low-power stop mode.
0 No wake interrupt requested.
1 When the FlexCAN is in low-power stop mode and a recessive to dominant transition is 

detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an 
interrupt request is generated. 

15

14

13

12

11

10

9

8

Field

BUF15M

BUF14M

BUF13M

BUF12

BUF11M

BUF10M

BUF9M

BUF8M

Reset

0000_0000

R/W

R/W

7

6

5

4

3

0

Field

BUF7M

BUF6M

BUF5M

BUF4M

BUF3M

BUF2M

BUF1M

BUF0M

Reset

0000_0000

R/W

R/W

Address

IPSBAR + 0x1C_0022