Motorola MCF5281 用户手册

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Chapter 27.  Queued Analog-to-Digital Converter (QADC)  

27-19

This subsection describes the QADC status registers.

QASR0 contains information about the state of each queue and the current A/D conversion.
The bits in this register are read anytime. For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2),
writing a 1 has no effect; writing a 0 clears the bit. For QS[9:6] and CWP, writes have no
effect. Stop mode resets this register.

The end of a queue is identified in the following cases:

• When execution is complete on the CCW in the location prior to the one 

pointed to by BQ2

01011

Interval timer single-scan mode: time = QCLK period x 2

14

01100

Interval timer single-scan mode: time = QCLK period x 2

15 

01101

Interval timer single-scan mode: time = QCLK period x 2

16 

01110

Interval timer single-scan mode: time = QCLK period x 2

17 

01111

Reserved mode 

10000

Reserved mode 

10001

Software triggered continuous-scan mode 

10010

Externally triggered rising edge continuous-scan mode 

10011

Externally triggered falling edge continuous-scan mode 

10100

Periodic timer continuous-scan mode: time = QCLK period x 2

7 

10101

Periodic timer continuous-scan mode: time = QCLK period x 2

8 

10110

Periodic timer continuous-scan mode: time = QCLK period x 2

9 

10111

Periodic timer continuous-scan mode: time = QCLK period x 2

10 

11000

Periodic timer continuous-scan mode: time = QCLK period x 2

11 

11001

Periodic timer continuous-scan mode: time = QCLK period x 2

12 

11010

Periodic timer continuous-scan mode: time = QCLK period x 2

13 

11011

Periodic timer continuous-scan mode: time = QCLK period x 2

14 

11100

Periodic timer continuous-scan mode: time = QCLK period x 2

15 

11101

Periodic timer continuous-scan mode: time = QCLK period x 2

16 

11110

Periodic timer continuous-scan mode: time = QCLK period x 2

17 

11111

Reserved mode