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Chapter 27.  Queued Analog-to-Digital Converter (QADC)  

27-35

Total conversion time is made up of initial sample time, final sample time, and resolution
time. Initial sample time refers to the time during which the selected input channel is
coupled through the sample buffer amplifier to the sample capacitor. The sample buffer is
used to quickly reproduce its input signal on the sample capacitor and minimize charge
sharing errors. During the final sampling period the amplifier is bypassed, and the
multiplexer input charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is converted to a digital
value and stored in the SAR as shown in Figure 27-20.

Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is 10
QCLK cycles.

A conversion requires a minimum of 14 QCLK cycles (7 

µs with a 2.0-MHz QCLK). If the

maximum final sample time period of 16 QCLKs is selected, the total conversion time is
28 QCLKs or 14 

µs (with a 2.0-MHz QCLK).

PQA4

PQA0

PQB3

PQB0

V

DDA

V

SSA

V

RH

V

RL

QCLK

Start Conv
End OF Conv

RST

STOP

SAR[9:0]

10-bit A/D Converter

Input

Analog

Power

2

IST

Sample

Compar-

Successive

ator

Bias Circuit

Approximation

Register

Buffer

10

10

CHAN[5:0]

 

CSAMP

10

Chan. Decode & MUX

16:1

Signals From/to Qu

eue Contr

ol 

Logic

16

State Machine & Logic

Power-

Down

Internal

Channel

Decode

SAR Timing

4

6