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Chapter 27.  Queued Analog-to-Digital Converter (QADC)  
27-43
Digital Control Subsystem
Figure 27-26. CCW Priority Situation 4
Situation S5 (Figure 27-27) shows that when multiple queue 2 trigger events are detected
while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not
disturbed. Situation S5 also shows that the effect of queue 2 trigger events during queue 1
execution is the same when the pause feature is used for either queue.
 
Figure 27-27. CCW Priority Situation 5
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event
occurring during queue 2 execution. Because queue 1 has higher priority, the conversion
taking place in queue 2 is aborted so that there is no variable latency time in responding to
queue 1 trigger events.
In situation 6 (Figure 27-28), the conversion initiated by the second CCW in queue 2 is
aborted just before the conversion is complete, so that queue 1 execution can begin. Queue
2 is considered suspended. After queue 1 is finished, queue 2 starts over with the first CCW,
Q1:
Q2:
QS:
IDLE
IDLE
 ACTIVE 
IDLE
0000
1000
0010
 ACTIVE  
0000
C1
C2
C3
C4
T1
Q1:
CF1
Q2:
C1
C2
C3
C4
T2
CF2
IDLE
1011
 TRIGGERED 
Q1:
Q2:
QS:
IDLE
IDLE
IDLE
0000
1000
0010
 ACTIVE  
0000
C1
C2
T1
Q1:
C1
C2
PF2
C3
C4
C3
C4
CF2
IDLE
1011
 TRIG 
Q2: 
T2
T2
PF1
 PAUSE  
 ACTIVE  
 PAUSE  
TOR2
T2
T2
CF1
TOR2
T1
 ACTIVE  
 TRIG 
0110
 ACTIVE  
 ACTIVE  
0101 1001 1011